CY2410 Cypress Semiconductor Corp., CY2410 Datasheet - Page 3

• Manufacturer Part Number: CY2410
• Description: Mpeg With Vcxo
• Manufacturer: Cypress Semiconductor Corp.

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The CY2410-3 utilizes a two-wire-interface SDAT and SCLK
that operates up to 400 kbits/sec in Read or Write mode. The
basic Write serial format is as follows: start bit; 7-bit device
address (DA); R/W bit; slave clock acknowledge (ACK); 8-bit
memory address (MA); ACK; 8-bit data; ACK; 8-bit data in
MA+1 if desired; ACK; 8-bit data in MA+2; ACK; etc. until stop
bit, as illustrated in Figure 1.
Data Valid
Data is valid when the clock is HIGH, and may only be transi-
tioned when the clock is low as illustrated in Figure 2.
Data Frame
Every new data frame is indicated by a start and stop
sequence, as illustrated in Figure 3.
Start Sequence
A start frame is indicated by SDAT going LOW when SCLK is
HIGH. Every time a start signal is given, the next 8-bit data
must be the device address (7 bits) and a R/W bit (0 for Write),
followed by register address (8 bits) and register data (8 bits).
See Figure 3.
Stop Sequence
A stop frame is indicated by SDAT going HIGH when SCLK is
HIGH. A stop frame frees the bus for writing to another part on
the same bus or writing to another random register
address. See Figure 3.
Acknowledge Pulse
During Write mode, the CY2410-3 will respond with an ACK
pulse after every 8 bits. This is accomplished by pulling the
SDAT line LOW during the next clock cycle after the eighth bit
is shifted in.
Device Address
The 7-bit device address is 1101001.
Register Address
The 8-bit address for the VCXO register is 00010011.
Register Data
The register data can be any value between 00H–FFH. As you
increase the value, the capacitance on the X
will increase, thereby decreasing the xtal frequency.
Document #: 38-07317 Rev. *B
SDA Write
rial Programmable Interface Protocol
Start Signal
Figure 1. Data Frame Architecture
Device
Address
R/W = 0
7-bit
1-bit
Slave
1-bit
ACK
Register
Address
8-bit
1-bit
Slave
ACK
Register
Data
8-bit
IN
1-bit
Slave
ACK
and X
Stop Signal
OUT
pins
SDAT
SCLK
SDAT
SCLK
Figure 5. Rise and Fall Time Definitions: ER = 0.6 x
V
V
IH
IL
CLK
Figure 2. Data Valid and Data Transition Periods
START
Figure 4. Duty Cycle Definition; DC = t2/t1
CLK
Figure 3. Start and Stop Frame
Data Valid
CLK
VDD / t3, EF = 0.6 x VDD / t4
HIGH
50%
t1
t2
t3
Transition
t
to next bit
80%
20%
DH
CLK
Transition
to next bit
LOW
50%
t
SU
t4
CY2410
STOP
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