tda8025hn NXP Semiconductors, tda8025hn Datasheet - Page 12

• Manufacturer Part Number: tda8025hn
• Description: Ic Card Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8025_1
Product data sheet
The duty cycle on pin CLK should be between 45 % and 55 %. To ensure this, the
following must be applied:
The clock signal is applied to the card based on the activation sequence as shown on the
timing diagrams; see
When the signal applied to XTAL1 is controlled by the microcontroller, the clock signal is
sent to the card only after the activation sequence finishes.
Table 4.
Clock circuitry definition (pins CLKDIV1 and CLKDIV2 can be changed simultaneously; a
>10 XTAL1 period delay is needed. The minimum duration of any CLK state is 10 XTAL1 periods).
CLKDIV1
0
0
1
1
Fig 6.
•
•
when the CLK frequency is f
If an external clock is connected to pin XTAL1, the duty cycle should be between 48 %
and 52 % with an input signal period transition time of less than 5 %.
If a crystal is used to generate f
45 % and 55 % depending on the layout, crystal characteristics and frequency.
when CLK frequency is either f
The duty cycle is guaranteed between 45 % and 55 % of the period frequency
divisions.
When a crystal is used, it runs when pin ENCLKIN is driven LOW.
(1) External crystal (optional).
Clock circuits
Clock configuration
Figure 8 on page 15
Rev. 01 — 6 April 2009
ENCLKIN
CLKDIV1
CLKDIV2
CLKDIV2
0
1
1
0
xtal
xtal
:
6
5
26
xtal
,
, the duty cycle on pin CLK should be between
1
MULTIPLEXER
OSCILLATOR
2
XTAL
27
XTAL2
CIRCUIT
f
CLOCK
26 MHz (1)
xtal
to
Figure 13 on page
,
1
4
f
xtal
28
XTAL1
or
15 CLK
001aai963
1
8
f
xtal
CLK
1
1
1
f
xtal
8
4
2
:
f
f
f
xtal
xtal
xtal
19.
TDA8025
© NXP B.V. 2009. All rights reserved.
IC card interface
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