tda8374bh NXP Semiconductors, tda8374bh Datasheet - Page 42

• Manufacturer Part Number: tda8374bh
• Description: Tda837x Family I?c-bus Controlled Economy Pal/ntsc And Ntsc Tv-processors
• Manufacturer: NXP Semiconductors

Philips Semiconductors
26. When the colour decoder is forced to a fixed subcarrier frequency (via the XA/XB or the CM bits) the chroma trap is
27. The 3 dB bandwidth of the circuit can be calculated using the following equation:
28. Valid for a signal amplitude on the Y input of 0.7 V (black-to-white) (100 IRE) with a rise time (10% to 90%) of 70 ns
29. For video signals with a black level which deviates from the back porch blanking level the signal is ‘stretched’ to the
30. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing
31. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
32. The ICs have 2 protection inputs.
1997 Jul 01
I
and NTSC TV-processors
2
always switched on, also when no colour signal is identified. When 2 crystals are active the chroma trap is switched
off when no colour signal is identified.
and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the
overshoots but by measuring the frequency response of the Y output.
blanking level. The amount of correction depends on the IRE value of the signal (see Fig.17). The black level is
detected by means of an external capacitor. The black level stretcher can be made inoperative by connecting the pin
to ground. The values given are valid only when the luminance input signal has an amplitude of 1 V (p-p).
level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync
separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is
4 V (p-p).
switched depending on the input signal condition and the condition of the bus. Therefore the circuit contains a noise
detector and the time constant is switched to ‘slow’ when too much noise is present in the signal. In the ‘fast’ mode,
during the vertical retrace time, the phase detector current is increased by 50% so that phase errors due to the head
switching of the VCR are corrected as soon as possible. Switching between the two modes can be made
automatically or overruled by the bus (see Tables 4, 6, 8 and 10).
The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be
used to close or open the first control loop when a video signal is present or not on the input. This ensures a stable
On-Screen-Display (OSD) when just noise is present at the input. The coupling of the video identification circuit with
the first loop can be overruled via the I
circuit is only active for ‘internal’ CVBS signals.
To prevent the horizontal synchronization being disturbed by anti-copy guard signals, such as Macrovision, the
phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output
voltage. The width of the gate pulse is approximately 22 s. Furthermore the phase detector is gated during the lower
part of the picture (pulse width = 12 s) to prevent disturbances due to overmodulated subtitles. The latter gating is
active only with standard signals (number of lines per frame 625 or 525). During weak signal conditions (noise
detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to
5.7 s so that the effect of the noise is reduced to a minimum. The output current of the phase detector in the various
conditions are given in Table 57.
The protection at pin 42 is intended to be used as ‘flash’ protection. When this protection is activated the horizontal
drive is switched off immediately and then switched on again via the slow start procedure.
The protection on pin 50 is intended for overvoltage (X-ray) protection. When this protection is activated the
horizontal drive can be switched off directly (via the slow stop procedure). It is also possible to continue the horizontal
drive and to set the protection bit (XPR) in the output bytes of the I
operation is made with the PRD bit.
f
C-bus controlled economy PAL/NTSC
–
3 dB
=
f
osc
1
–
------- -
2Q
1
2
C-bus. The coupling between the phase 1 detector and the video identification
42
2
C-bus. The choice between the 2 modes of
TDA837x family
Preliminary specification