tda8361 NXP Semiconductors, tda8361 Datasheet - Page 25

• Manufacturer Part Number: tda8361
• Description: Integrated Pal And Pal/ntsc Tv Processors
• Manufacturer: NXP Semiconductors

Philips Semiconductors
28. The amplitude response curve can be expressed as follows:
29. Slicing level independent of sync pulse amplitude.
30. The horizontal and vertical sync are stable while processing Copy Guard signals and signals with phase shifted sync
31. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
32. Picture shift can be obtained by means of a variable external load on the second phase detector. The control range
33. The vertical blanking pulse in the RGB outputs has a width of 22 or 17.5 lines (50 or 60 Hz system). The width of the
34. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit.
35. This precorrection is intended to compensate for non-linearity of AC coupled vertical output stages. The value given
36. At a chrominance input voltage (related to CVBS2) of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal
March 1994
Integrated PAL and PAL/NTSC TV
processors
A(f) = 1 + K1
and is realised with a transversal peaking filter having delay sections of 160 ns each. In the ‘neutral’ setting K = 0
and in the minimum setting K = 0.5.
The peaking signal amplifier is linear for 250 ns step input signals up to 50 IRE units. For higher amplitudes the
marginal gain is reduced. When the horizontal PLL is not synchronized (no signal present at the video input) the
peaking control voltage is pulled down by means of an internal current. This information can be used to detect
whether an input signal is available.
pulses (stretched tapes). Trick mode conditions of the VCR will also not disturb the synchronization. The value given
is the delay caused by the vertical sync pulse integrator. The integrator has been designed such that the vertical sync
is not disturbed for special anti-copy tapes with vertical sync pulses with an on/off time of 10/22 s.
switched depending on the input signal condition. Therefore the circuit contains a noise detector and the time
constant is switched to ‘slow’ when excessive noise is present in the signal (only when the internal video signal is
selected, when the video switch is in the external mode the time constant is always ‘fast’). In the ‘fast’ mode during
the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of
the VCR are corrected as soon as possible.
When no video signal is received the time constant of the first loop is switched to ‘very slow’. This ensures a stable
OSD when the receiver is switched to a channel without transmitter.
The output current of the phase detector for the various conditions is shown in Table 2.
is 2 s; the required current for this phase shift is 6 A.
vertical sync pulse in the sandcastle pulse is 14 lines. This is to prevent a phase distortion on top of the picture due
to a timing modulation of the incoming flyback pulse.
This divider circuit has 2 search modes of operation:
The ‘large window’ mode is switched on when the circuit is not synchronized or, when a non-standard signal is
received (the number of lines per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between
261 and 264). In the search mode the divider can be triggered between line 244 and line 361 (approximately
45 to 64.5 Hz)
The ‘narrow window’ mode is switched on when more than 15 successive vertical sync pulses are detected in the
narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the
vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small.
The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found
within the window.
indicates the amplitude of the correction waveform with respect to the sawtooth amplitude.
amplitude 300 mV (p-p)) the dynamic range of the ACC is +6 and 20 dB.
cos (180 x f/3.1 MHz)
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TDA8360; TDA8361; TDA8362
Objective specification