hi5714 Intersil Corporation, hi5714 Datasheet
hi5714
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hi5714 Summary of contents
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... The HI5714 is optimized for a wide range of applications such as ultrasound imaging, mass storage, instrumentation, and video digitizing, where accuracy and low power consumption are essential. The HI5714 is offered in 40 MSPS, 60 MSPS, and 75 MSPS sample rates. The HI5714 delivers ±0.4 LSB differential nonlinearity while consuming only 325mW power (Typical MSPS ...
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... TTL OUTPUTS CCO1 V CCO2 21 O/UF 11 TTL OUTPUT HI5714 11 O/ CCO 21 V CCO 18 V +5VD CCD 1nF 0.1µF 20 OGND DGND 10 NC 1nF and 0.1µF CAPS are placed as close to part as possible. ...
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... Operating Conditions Temperature Range HI5714/XCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...
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... Spurious Free Dynamic Range, SFDR Analog Input Bandwidth (-3dB) TRANSFER FUNCTION Differential Linearity Error, DNL Integral Linearity Error, INL EFFECTIVE NUMBER OF BITS ENOB HI5714 40MHz) CLK HI5714 75MHz) CLK Bit Error Rate, BER TIMING (f = 75MHz) See Figures 1, 2 CLK Sampling Delay Output Hold Time, t ...
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... Full scale sinewave 4.43MHz ±8 LSB at code 128, 50% Clock duty cycle 75MHz 4.43MHz, V CLK Parameter is guaranteed by design, not production tested. 5 HI5714 = +5V 1.3V 3.6V; T CCD CCO RB RT TEST CONDITION may have any value between -0.3V and +6V as long as the difference V ...
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... Timing Waveforms CLOCK INPUT ANALOG INPUT DATA (D0-D7) OUTPUTS INPUT DIGITAL OUTPUT DIGITAL OUTPUT 6 HI5714 t CPL t CPH SAMPLE SAMPLE FIGURE 1. INPUT-TO-OUTPUT TIMING OE 1.4V t PZL t PHZ t PZH FIGURE 2. THREE-STATE TIMING CIRCUIT 1.4V SAMPLE 2.4V 1. ...
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... TEMPERATURE ( FIGURE 5. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE -220 -230 -240 -250 -260 -270 -280 -290 -300 -310 -320 -40 -30 -20 - TEMPERATURE ( FIGURE TEMPERATURE OT 7 HI5714 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 FIGURE 4. INTEGRAL LINEARITY ERROR vs TEMPERATURE 280 270 260 250 240 230 ...
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... The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage, including the typical reference offset voltages HI5714 DESCRIPTION Digital Outputs, D0 (LSB (MSB). Bottom Reference Voltage Input. Range: 1.2V to 1.6V. Analog Ground. Analog +5V. ...
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... Digital Outputs and O/UF Output The digital outputs are standard TTL type outputs. The HI5714 can drive TTL inputs depending on the input current requirements. Should the analog input exceed the top or bottom reference the over/underflow output (pin 11) will go high ...
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... FIGURE 10. TYPICAL DC COUPLED INPUT HI5714 CCO 21 V CCO 18 +5VD V CCD 10 0.1 20 OGND DGND HI5714 CCO 21 V CCO 18 +5VD V CCD 10 0.1 20 OGND DGND 10 NC ...
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... ICL8069 REFERENCE AMP HA5020 (Single) HI5714 (8-Bit) HA5022 (Dual) HA5024 (Quad) HA5013 (Triple) HFA1105 (Single) HFA1205 (Dual) HFA1405 (Quad) HSP9501: Programmable Data Buffer HSP48410: Histogrammer/accumulating Buffer, 10-Bit Pixel Resolution Frame Size HSP48908: 2-D Convolver Kernal Convolution, 8-Bit HSP48901 Image Filter, 30MHz, 8-Bit ...
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... Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5714. A low distortion sine wave is applied to the input sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 2048 point FFT and analyzed to evaluate the dynamic performance of the A/D ...
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... CCA O/UF 13 HI5714 PASSIVATION: Type: Sandwich Passivation* Undoped Silicon Glass Thickness: USG - 8k Total 12.2k WORST CASE CURRENT DENSITY TRANSISTOR COUNT: 3714 DIE ATTACH: Silver Filled Epoxy HI5714 (USG) + Nitride Å Å , Nitride - 4.2k Å Å A/ CC02 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 HI5714 M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE ...