CY25811/12/14 Cypress Semiconductor Corp., CY25811/12/14 Datasheet - Page 3

• Manufacturer Part Number: CY25811/12/14
• Description: Emi Suppression
• Manufacturer: Cypress Semiconductor Corp.

Document #: 38-07112 Rev. *C
Table 2. Spread% Selection (continued)
3–Level Digital Inputs
S0, S1, and FRSEL digital inputs are designed to sense 3
different logic levels designated as High “1”, Low “0” and
Middle “M”. With this 3-Level digital input logic, the 3-Level
Logic is able to detect 9 different logic states.
S0, S1 and FRSEL pins include an on chip 20K (10K /10K)
resistor divider. No external application resistors are needed
to implement the 3-Level logic levels as shown below:
Logic Level “0”: 3–Level logic pin connected to GND.
Logic Level “M”: 3–Level logic pin left floating (no connection.)
Logic Level “1”: 3–Level logic pin connected to V
Figure 1 illustrates how to implement 3–Level Logic.
Modulation Rate
Spread Spectrum Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (fmax) and
minimum frequency of the clock (fmin) determine this band of
frequencies. The time required to transition from fmin to fmax
and back to fmin is the period of the Modulation Rate. The
Modulation Rate of SSCG clocks are generally referred to in
terms of frequency, or
fmod = 1/Tmod.
The input clock frequency, fin, and the internal divider
determine the Modulation Rate.
In the case of CY25811/2/4 devices, the (Spread Spectrum)
modulation Rate, fmod, is given by the following formula:
fmod = fin/DR
(MHz)
24-28
28-32
XIN
FRSEL
M
M
S1 = 0
S0 = 0
±1.2
±1.1
FRSEL
to VSS
LOW (0)
S0, S1
LOGIC
and
S0 = M
S1 = 0
± 0.9
± 0.9
VSS
S1 = 0
S0 = 1
DD
± 0.5
± 0.4
UNCONNECTED
Figure 1. 3–Level Logic
.
MIDDLE (M)
FRSEL
S0, S1
and
LOGIC
S1 = M
S0 = 0
± 0.4
± 0.3
Where; fmod is the Modulation Rate, fin is the Input Frequency
and DR is the Divider Ratio as given in Table 3. Notice that
Input Frequency Range is set by FRSEL.
Table 3. Modulation Rate Divider Ratios
Input and Output Frequency Selection
The relationship between input frequency versus output
frequency in terms of device selection and FRSEL setting is
given in Table 4. As shown, the input frequency range is
selected by FRSEL and is the same for CY25811, CY25812,
and CY25814. The selection of CY25811 (1x), CY25812 (2x)
or CY25814 (4x) determines the frequency multiplication at
the output (SSCLK, Pin 5) with respect to input frequency
(XIN, Pin-1).
FRSEL
M
0
1
S1 = 1
S0 = 1
–2.5
–2.3
Input Frequency Range
HIGH (H)
S1 = 1
S0 = 0
–1.8
–1.7
LOGIC
FRSEL
to VDD
S0, S1
and
16 to 32
8 to 16
(MHz)
4 to 8
S1 = M
S0 = 1
–1.5
–1.4
CY25811/12/14
S0 = M
S1 = 1
–0.6
–0.5
Divider Ratio
Page 3 of 10
(DR)
128
256
512
S1 = M
S0 = M
0
0