hi7191 Intersil Corporation, hi7191 Datasheet - Page 20

• Manufacturer Part Number: hi7191
• Description: 24-bit, High Precision, Sigma Delta A/d Converter
• Manufacturer: Intersil Corporation

Control Register
The Control Register contains 24-bits to control the various
sections of the HI7191. This register is a read/write register.
DC - Bit 23 is the Data Coding Bit used to select between
two’s complementary and offset binary data coding. When
this bit is set (DC = 1) the data in the Data Output Register
will be two’s complement. When cleared (DC = 0) this data
will be offset binary. When operating in the unipolar mode
the output data is available in straight binary only (the DC bit
is ignored). This bit is cleared after a RESET is applied to the
part.
FP10 through FP0 - Bits 22 through 12 are the Filter
programming bits that determine the frequency response of
the digital filter. These bits determine the filter cutoff
frequency, the position of the first notch and the data rate of
the HI7191. The first notch of the filter is equal to the
decimation rate and can be determined by the formula:
MSB
FP3
DC
G2
SDIO
15
SCLK
SCLK
SDO
7
SDIO
SDO
CS
CS
FP10
FP2
G1
I0
22
14
6
I0
I1
FP9
FP1
I1
G0
21
13
5
I2
IR WRITE PHASE
IR WRITE PHASE
I2
THREE-STATE
I3
FP8
FP0
THREE-STATE
BO
20
12
I3
4
I4
BYTE 2
BYTE 1
BYTE 0
FIGURE 19. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE HIGH
FIGURE 18. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE LOW
20
I4
I5
MD2
FP7
SB
19
11
3
I5
I6
I6
I7
MD1
FP6
BD
18
10
2
I7
MD0
MSB
FP5
17
9
1
B0
B0
LSB
SDL
FP4
B/U
B1
16
8
B1
B2
HI7191
B2
B3
B3
B4
f
where CODE is the decimal equivalent of the value in FP10
through FP0. The values that can be programmed into these
bits are 10 to 2047 decimal, which allows a conversion rate
range of 9.54Hz to 1.953kHz when using a 10MHz clock.
Changing the filter notch frequency, as well as the selected
gain, impacts resolution. The output data rate (or effective
conversion time) for the device is equal to the frequency
selected for the first notch to the filter. For example, if the
first notch of the filter is selected at 50Hz then a new word is
available at a 50Hz rate or every 20ms. If the first notch is at
1kHz a new word is available every 1ms.
The settling-time of the converter to a full scale step input
change is between 3 and 4 times the data rate. For example,
with the first filter notch at 50Hz, the worst case settling time
to a full scale step input change is 80ms. If the first notch is
1kHz, the settling time to a full scale input step is 4ms
maximum.
The -3dB frequency is determined by the programmed first
notch frequency according to the relationship:
f
MD2 through MD0 - Bits 11 through 9 are the Operational
Modes of the converter. See Table 4 for the Operational
Modes description. After a RESET is applied to the part
these bits are set to the self calibration mode.
B/U - Bit 8 is the Bipolar/Unipolar select bit. When this bit is
set the HI7191 is configured for bipolar operation. When this
bit is reset the part is in unipolar mode. This bit is set after a
RESET is applied to the part.
NOTCH
B4
-3dB
DATA TRANSFER PHASE - TWO-BYTE READ
B5
DATA TRANSFER PHASE - TWO-BYTE READ
B5
= 0.262 x f
B6
= f
THREE-STATE
B6
OSC
B7
THREE-STATE
/(512 x CODE)
NOTCH
B7
B8
.
B8
B9
B9
B10 B11 B12 B13 B14
B10 B11 B12 B13 B14
B15
June 1, 2006
B15
FN4138.8