clc5958 National Semiconductor Corporation, clc5958 Datasheet
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clc5958
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clc5958 Summary of contents
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... Other features include differential analog inputs, low jitter differential clock inputs, an internal bandgap voltage reference, and CMOS/TTL compatible outputs. The CLC5958 is fabricated on the National ABIC-V 0.8 micron BiCMOS process. The CLC5958 features a 90dB spurious free dynamic range (SFDR) and a 70dB signal to noise ratio (SNR). The balanced ...
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... CLC5958 Electrical Characteristics PARAMETERS RESOLUTION DIFF. INPUT VOLTAGE RANGE MAXIMUM CONVERSION RATE SNR SFDR SFDR EXCLUDING 2nd & 3rd HARM. NO MISSING CODES NOISE AND DISTORTION noise floor f = 5MHz 5MHz in 2nd & 3rd harmonic distortion (w/o dither 5MHz 20MHz 70MHz ...
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... Package Thermal Resistance 5sec Package 48-pin CSP Package Transistor Count Transistor count Ordering Information 48-pin CSP (industrial temperature range) Fully loaded evaluation board with CLC5958 … ready for test -40° +85°C) min max RATINGS UNITS MIN ...
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... CLC5958 Typical Performance Characteristics Single-Tone Output Spectrum 0 -20 -40 -60 -80 -100 -120 0 5 Frequency (MHz) Single-Tone Output Spectrum (w/Dither) 0 -20 -40 Dither -60 -80 -100 -120 0 5 Frequency (MHz) Two-Tone Output Spectrum 0 f1 -20 -40 -60 -80 f2-f1 -100 -120 0 5 Frequency (MHz) Differential Non-Linearity 1.0 0.6 0.2 -0.2 -0.6 -1.0 0 4000 http://www.national.com (V = +5V, 52MSPS ...
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... CLC5958 Typical Performance Characteristics Noise and Spurious vs. Amplitude 120 110 Other Spurious 100 90 80 Noise Floor 70 60 -70 -60 -50 -40 Amplitude (dBFS) Noise and Spurious vs. Amplitude 120 110 100 90 Other Spurious 80 Noise Floor 70 60 -70 -60 -50 -40 Amplitude (dBFS) Noise and Distortion vs. Sample Rate ...
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... F capacitor. DV (Pins 37, 38) +3.3V to +5V power supply for the digital CC outputs. Establishes the high output level for the digital outputs. Bypass to ground with a 0.1 F capacitor. CLC5958 Block Diagram Summing Network 4-bit 4-bit Flash DAC Over-range Correction Logic & Output Buffers ...
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... CLC5958 Package Dimensions 7 http://www.national.com ...
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... This bias voltage is set for optimum performance, and varies with temperature. Since DC coupling the inputs overrides the internal common mode voltage recommended that the inputs to the CLC5958 be AC coupled whenever possible. The time constant of the input coupling network must be greater than 1 sec to minimize distortion due to nonlinear input bias currents ...
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... The clock is internally divided by the CLC5958 in order to generate internal control signals. These divided clocks can contribute spurious energy, principally at f The clock spurious is typically less than -90dBFS. ...
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... CLC5958. It illustrates the proper approach to layout in order to achieve best performance, and provides a performance benchmark. Analog Input The CLC5958 evaluation board is configured to be driven by a single-ended signal at the AIN SMA connector (the AIN connector is disconnected). The AIN SMA connector should be driven impedance ...
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... CLC5958 Evaluation Board Layout CLC5958PCASM Layer 1 CLC5958PCASM Layer 3 CLC5958PCASM Layer 2 CLC5958PCASM Layer 4 11 http://www.national.com ...
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... CLC5958 Evaluation Board Schematic http://www.national.com 12 ...
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... National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signifi ...