uda1335h NXP Semiconductors, uda1335h Datasheet - Page 10

• Manufacturer Part Number: uda1335h
• Description: Universal Serial Bus Usb Audio Playback Recording Peripheral Aprp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
The Analog-to-Digital Interface (ADIF)
The ADIF is used for sampling an analog input signal from
a microphone or line input and sending the audio samples
to the USB interface. The ADIF consists of a stereo
Programmable Gain Amplifier (PGA), a stereo
Analog-to-Digital Converter (ADC) and Decimation Filters
(DFs). The sample frequency of the ADC is determined by
the ADC clock (see Section “The timing of the
analog-to-digital interface”). The user can also select a
digital serial input instead of an analog input. In this event
the sample frequency is determined by the continuous WS
clock with a range between 5 to 55 kHz. Digital serial input
is possible with four formats (I
LSB-justified).
The Programmable Gain Amplifier circuit (PGA)
This circuit can be used for a microphone or line input.
The input audio signals can be amplified by 7 different
gains. The preferred gain is selected during start-up of the
device (configuration map).
The gain settings are given in Table 1.
Table 1 The selectable gains of the PGA
The Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1335H consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 128.
Both ADCs can be switched off in power saving mode (left
and right separate). The ADC clock is generated by the
analog PLL or the ADC oscillator.
1998 Aug 28
Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)
SETTING
000
001
010
100
101
11X
011
GAIN
15
21
27
0
3
9
3
2
S-bus, 16, 18 or 20 bits
UNIT
dB
dB
dB
dB
dB
dB
dB
10
The Decimation Filter (DF)
The decimator filter converts the audio data from 128f
down to 1f
will be transmitted over the USB as mono or stereo in
1, 2 or 3 bytes/sample. The decimator filters are clocked
by the ADC clock.
The timing of the analog-to-digital interface
The clock source of the ADIF is the analog PLL or the ADC
oscillator. The preferred clock source can be selected
during start-up of the device (configuration map). The ADC
clock used for the ADC and decimation filters is obtained
by dividing the clock signal coming from the analog PLL or
from the ADC oscillator by a factor Q.
Using the analog PLL the user can select 3 clock
frequencies via the microcontroller.
By connecting the appropriate crystal the user can choose
any clock signal between 8.192 and 14.08 MHz via the
ADC oscillator.
Table 2 The analog PLL clock output frequencies
The dividing factor Q can be selected via the
microcontroller. With this dividing factor Q the user can
select a range of ADC clock signals allowing several
different sample frequencies (see Table 3).
FCODE
00
01
10
11
s
with a word width of 8, 16 or 24 bits. This data
FREQUENCY (MHz)
APLL CLOCK
Preliminary specification
12.2880
11.2896
11.2896
8.1920
UDA1335H
s