uda1320ats NXP Semiconductors, uda1320ats Datasheet - Page 8

• Manufacturer Part Number: uda1320ats
• Description: Low-cost Stereo Filter Dac
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9
9.1
The following system and digital sound processing
features can be controlled in the microcontroller mode of
the UDA1320ATS/N2:
The exchange of data and control information between the
microcontroller and the UDA1320ATS/N2 is accomplished
through a serial hardware interface comprising the
following pins:
Information transfer through the microcontroller bus is
organized in accordance with the L3 format, in which two
different modes of operation can be distinguished; address
mode and data transfer mode (see Figs 4 and 6).
The address mode is required to select a device
communicating via the L3 bus and to define the
destination registers for the data transfer mode.
2000 Jan 10
handbook, full pagewidth
System clock frequency
Data input format
De-emphasis for 32 kHz, 44.1 kHz and 48 kHz
Volume
Soft mute.
L3DATA
L3MODE
L3CLOCK.
Low-cost stereo filter DAC
L3 INTERFACE DESCRIPTION
The L3 interface
L3MODE
L3CLCK
L3DATA
t h(L3)A
BIT 0
t su(L3)A
t su(L3)DA
Fig.4 Timing address mode.
t CLK(L3)H
t CLK(L3)L
8
Data transfer can only be in one direction, consisting of
input to the UDA1320ATS/N2 to program sound
processing and other functional features.
Data bits 7 to 2 represent a 6-bit device address, bit 7
being the MSB. The address of the UDA1320ATS/N2 is
000101 (bit 7 to bit 2). If the UDA1320ATS/N2 receives a
different address, it will deselect its microcontroller
interface logic.
9.2
The selected address remains active during subsequent
data transfers until the UDA1320ATS/N2 receives a new
address command. The fundamental timing of data
transfers is essentially the same as in the address mode,
see Fig.6. The maximum input clock and data rate is 64 f
All transfers are by 8-bit bytes. Data will be stored in the
UDA1320ATS/N2 after reception of a complete byte. See
Fig.5 for a multi-byte transfer.
Table 4 Selection of data transfer
BIT 1
0
0
1
1
t h(L3)DA
Data transfer mode
BIT 0
0
1
0
1
DATA (volume, de-emphasis, mute)
not used
STATUS (system clock frequency,
data input format)
not used
T cy(CLK)(L3)
BIT 7
t su(L3)A
t h(L3)A
TRANSFER
Preliminary specification
UDA1320ATS
MBK072
s
.