uda1340 NXP Semiconductors, uda1340 Datasheet - Page 6

• Manufacturer Part Number: uda1340
• Description: Low-voltage Low-power Stereo Audio Codec With Dsp Features
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
System clock
The UDA1340 accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable. The options are 256f
The system clock must be locked in frequency to the digital
interface input signals.
Multiple format input/output interface
The UDA1340 supports the following data input/output
formats:
The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed.
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1340 consists of two
third-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.
Decimation filter (ADC)
The decimation from 128f
The first stage realizes 3rd-order
filter decreases the sample rate by 16. The second stage,
an FIR filter, consists of 3 half-band filters, each
decimating by a factor of 2.
Table 1 Decimation filter characteristics
1997 Jul 09
Passband Ripple
Stop band
Dynamic range
Gain
I
MSB justified serial format with data word length of up to
20 bits
LSB justified serial format with data word lengths of
16, 18 or 20 bits.
Low-voltage low-power stereo audio
CODEC with DSP features
2
S-bus with data word length of up to 20 bits
ITEM
CONDITION
s
0
0
>0.55f
is performed in two stages.
overall
0.45f
0.45f
s
sin x
----------- -
, 384f
s
s
s
x
characteristic. This
s
and 512f
VALUE (dB)
108
0.05
1.16
60
s
.
6
DC cancellation filter (ADC)
An optional IIR high-pass filter is provided to remove
unwanted DC components. The operation is selected by
the microcontroller via the L3-bus. The filter characteristics
are given in Table 2.
Table 2 DC cancellation filter characteristics
Mute (ADC)
On recovery from power-down or switching on of the
system clock, the serial data output DATAO is held LOW
until valid data is available from the decimation filter. This
time depends on whether the DC cancellation filter is
selected:
Overload detection (ADC)
In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than 1 dB (actual figure is 1.16 dB) of the maximum
possible digital swing. When this condition is detected the
OVERFL output is forced HIGH for at least 512f
(11.6 ms at f
infringement.
Passband ripple
Passband gain
Droop
Attenuation at DC
Dynamic range
DC cancel off: time =
f
DC cancel on: time =
f
s
s
= 44.1 kHz
= 44.1 kHz
ITEM
s
= 44.1 kHz). This time-out is reset for each
at 0.00000036f
CONDITION
1024
------------ -
12288
--------------- -
at 0.00045f
0
f
s
f
s
0.45f
, t = 23.2 ms when
, t = 279 ms when
Preliminary specification
s
s
s
UDA1340
VALUE (dB)
0.031
none
>110
>40
s
0
cycles