pca9545ad NXP Semiconductors, pca9545ad Datasheet - Page 10

• Manufacturer Part Number: pca9545ad
• Description: 4-channel I2c Switch With Interrupt Logic And Reset
• Manufacturer: NXP Semiconductors

NXP Semiconductors
7. Characteristics of the I
PCA9545A_45B_45C_6
Product data sheet
7.1 Bit transfer
7.2 START and STOP conditions
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the
STOP condition (P) (see
Fig 10. Bit transfer
Fig 11. Definition of START and STOP conditions
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
START condition
2
SDA
SCL
C-bus
S
Rev. 06 — 19 March 2007
Figure
4-channel I
11).
data valid
data line
stable;
Figure
2
C-bus switch with interrupt logic and reset
allowed
change
of data
PCA9545A/45B/45C
10).
STOP condition
mba607
P
© NXP B.V. 2007. All rights reserved.
mba608
SDA
SCL
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