pca9548ad NXP Semiconductors, pca9548ad Datasheet - Page 10

• Manufacturer Part Number: pca9548ad
• Description: 8-channel I2c Switch With Reset
• Manufacturer: NXP Semiconductors

Philips Semiconductors
PCA9548A_2
Product data sheet
Fig 10. System configuration
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
7.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; setup and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 11. Acknowledgement on the I
RECEIVER
SLAVE
SCL from master
by transmitter
data output
by receiver
data output
Rev. 02 — 25 September 2006
TRANSMITTER/
RECEIVER
condition
START
SLAVE
S
2
C-bus
TRANSMITTER
1
MASTER
2
8-channel I
TRANSMITTER/
RECEIVER
MASTER
acknowledgement
not acknowledge
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
SLAVE
clock pulse for
acknowledge
8
2
C-bus switch with reset
PCA9548A
MULTIPLEXER
002aaa987
I
2
9
C-BUS
002aaa966
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