pca9542pw NXP Semiconductors, pca9542pw Datasheet - Page 11
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pca9542pw
Manufacturer Part Number
pca9542pw
Description
2-channel I2c Multiplexer And Interrupt Controller
Manufacturer
NXP Semiconductors
Datasheet
1.PCA9542PW.pdf
(15 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PCA9542PW
Manufacturer:
NEC
Quantity:
7 321
Part Number:
PCA9542PW
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
1. Pass gate propagation delay is calculated from the 20
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH
3. C
Philips Semiconductors
AC CHARACTERISTICS
NOTES:
2004 Oct 01
SYMBOL
t
t
t
t
2-channel I
t
t
t
t
VD:DATH
VD:DATL
HD;STA
SU;STO
HD;DAT
SU;DAT
VD:ACK
the undefined region of the falling edge of SCL.
SU;STA
t
t
H
f
t
L
HIGH
LOW
INT
BUF
t
SCL
b
t
C
t
t
t
SP
t
pwr
pd
pwr
R
F
iv
ir
b
= total capacitance of one bus line in pF.
SDA
SCL
Propagation delay from SDA to SD
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Set-up time for STOP condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
Pulse width of spikes which must be suppressed
by the input filter
Data valid (HL)
Data valid (LH)
Data valid Acknowledge
INTn to INT active valid time
INTn to INT inactive delay time
LOW level pulse width rejection or INTn inputs
HIGH level pulse width rejection or INTn inputs
P
t
BUF
2
C multiplexer and interrupt logic
S
t
HD;STA
PARAMETER
t
LOW
t
t
Figure 13. Definition of timing on the I
R
HD;DAT
n
or SCL to SC
typical R
t
HIGH
n
ON
t
F
11
and and the 15 pF load capacitance.
t
SU;DAT
STANDARD-MODE
MIN
250
4.7
4.0
4.7
4.0
4.7
4.0
0.5
—
0
—
—
—
—
—
—
—
—
—
0
1
2
I
2
C-BUS
2
C-bus
Sr
MAX
1000
0.3
3.45
100
300
400
0.6
—
—
—
—
—
—
—
50
—
—
1
1
4
2
1
t
SU;STA
t
HD;STA
20 + 0.1C
20 + 0.1C
min
MIN
100
1.3
0.6
1.3
0.6
0.6
0.6
0.5
—
0
—
—
—
—
—
—
—
of the SCL signal) in order to bridge
FAST-MODE
0
1
2
I
2
C-BUS
b
b
3
3
t
SP
t
SU;STO
MAX
0.3
400
300
300
400
0.9
0.6
50
—
—
—
—
—
—
—
—
—
1
1
4
2
1
PCA9542
Product data sheet
SU00645
P
UNIT
kHz
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s