pca9535d NXP Semiconductors, pca9535d Datasheet - Page 8

• Manufacturer Part Number: pca9535d
• Description: 16-bit I2c And Smbus, Low Power I/o Port With Interrupt
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA9535_PCA9535C_3
Product data sheet
6.2.5 Registers 6 and 7: Configuration registers
6.3 Power-on reset
6.4 I/O port
This register configures the directions of the I/O pins. If a bit in this register is set (written
with ‘1’), the corresponding port pin is enabled as an input with high-impedance output
driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is
enabled as an output. At reset, the device's ports are inputs.
Table 11.
Table 12.
When power is applied to V
in a reset condition until V
released and the PCA9535/PCA9535C registers and SMBus state machine will initialize
to their default states. Thereafter, V
For a power reset cycle, V
operating voltage.
When an I/O is configured as an input on PCA9535, FETs Q1 and Q2 are off, creating a
high impedance input. The input voltage may be raised above V
In the case of PCA9535C, FET Q1 has been removed and the open-drain FET Q2 will
function the same as PCA9535.
If the I/O is configured as an output, then on PCA9535 either Q1 or Q2 is on, depending
on the state of the Output Port register. Care should be exercised if an external voltage is
applied to an I/O configured as an output because of the low-impedance path that exists
between the pin and either V
Bit
Symbol
Default
Bit
Symbol
Default
Configuration port 0 register
Configuration port 1 register
C0.7
C1.7
7
1
7
1
C0.6
C1.6
Rev. 03 — 4 October 2007
6
1
6
1
16-bit I
DD
DD
DD
DD
has reached V
must be lowered below 0.2 V and then restored to the
, an internal power-on reset holds the PCA9535/PCA9535C
or V
C0.5
C1.5
2
5
1
5
1
C-bus and SMBus, low power I/O port with interrupt
DD
SS
.
must be lowered below 0.2 V to reset the device.
C0.4
C1.4
POR
4
1
4
1
PCA9535; PCA9535C
. At that point, the reset condition is
C0.3
C1.3
3
1
3
1
C0.2
C1.2
DD
2
2
1
1
to a maximum of 5.5 V.
© NXP B.V. 2007. All rights reserved.
C0.1
C1.1
1
1
1
1
C0.0
C1.0
0
1
0
1
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