pca9539d NXP Semiconductors, pca9539d Datasheet - Page 6

• Manufacturer Part Number: pca9539d
• Description: 16-bit I2c And Smbus, Low Power I/o Port With Interrupt And Reset
• Manufacturer: NXP Semiconductors

Philips Semiconductors
REGISTERS
Command Byte
The command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.
Registers 0 and 1 — Input Port Registers
This register is an input-only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by Register 3. Writes to this register have no effect.
The default value ‘X’ is determined by the externally applied logic
level.
Registers 2 and 3 — Output Port Registers
This register is an output-only port. It reflects the outgoing logic
levels of the pins defined as outputs by Register 6 and 7. Bit values
in this register have no effect on pins defined as inputs. In turn,
reads from this register reflect the value that is in the flip-flop
controlling the output selection, NOT the actual pin value.
Registers 4 and 5 — Polarity Inversion Registers
This register allows the user to invert the polarity of the Input Port
register data. If a bit in this register is set (written with ‘1’), the Input
Port data polarity is inverted. If a bit in this register is cleared (written
with a ‘0’), the Input Port data polarity is retained.
Registers 6 and 7 — Configuration Registers
2006 Sep 21
16-bit I
I/O port with interrupt and reset
default
default
default
default
default
default
default
bit
Command
bit
bit
bit
bit
bit
bit
0
1
2
3
4
5
6
7
C0.7
O0.7
O1.7
N0.7
N1.7
I0.7
I1.7
1
1
1
X
X
0
0
2
C-bus and SMBus low power
C0.6
O0.6
O1.6
N0.6
N1.6
Register
I0.6
I1.6
Input port 0
Input port 1
Output port 0
Output port 1
Polarity inversion port 0
Polarity inversion port 1
Configuration port 0
Configuration port 1
1
1
1
X
X
0
0
C0.5
O0.5
O1.5
N0.5
N1.5
I0.5
I1.5
1
1
1
X
X
0
0
C0.4
O0.4
O1.4
N0.4
N1.4
I0.4
I1.4
1
X
X
1
1
0
0
C0.3
N0.3
N1.3
O0.3
O1.3
I0.3
I1.3
1
1
1
X
X
0
0
C0.2
O0.2
O1.2
N0.2
N1.2
I0.2
I1.2
1
X
X
1
1
0
0
C0.1
N0.1
N1.1
O0.1
O1.1
I0.1
I1.1
1
X
X
1
1
0
0
N0.0
N1.0
C0.0
IO.0
O0.0
O1.0
I1.0
X
X
1
1
1
0
0
6
This register configures the directions of the I/O pins. If a bit in this
register is set (written with ‘1’), the corresponding port pin is enabled
as an input with high impedance output driver. If a bit in this register
is cleared (written with ‘0’), the corresponding port pin is enabled as
an output. At reset the device’s ports are inputs.
POWER-ON RESET
When power is applied to V
PCA9539 in a reset condition until V
point, the reset condition is released and the PCA9539 registers and
SMBus state machine will initialize to their default states. Therefore,
V
For a power reset cycle, V
restored to the operating voltage.
RESET Input
A reset can be accomplished by holding the RESET pin LOW for a
minimum of t
machine will be held in their default state until the RESET input is
once again HIGH. This input typically requires a pull-up to V
DEVICE ADDRESS
default
DD
bit
must be lowered below 0.2 V to reset the device.
C1.7
1
W
. The PCA9539 registers and SMBus/I
C1.6
1
Figure 5. PCA9539 address
1
1
fixed
C1.5
DD
1
slave address
DD
1
must be lowered below 0.2 V and then
, an internal power-on reset holds the
0
C1.4
1
1
DD
A1
has reached V
programmable
C1.3
1
A0
SW02204
R/W
C1.2
PCA9539
1
Product data sheet
2
POR
C state
C1.1
1
. At that
DD
C1.0
.
1