pca9558pw NXP Semiconductors, pca9558pw Datasheet - Page 11

• Manufacturer Part Number: pca9558pw
• Description: 8-bit I2c And Smbus I/o Port With 5-bit Multiplexed/1-bit Latched 6-bit I2c Eeprom And 2 K Bit Eeprom
• Manufacturer: NXP Semiconductors

Philips Semiconductors
RESET
Power-on Reset (POR)
When power is applied to V
PCA9558 in a reset state until V
the reset condition is released and the PCA9558 volatile registers
and SMBus state machine will initialize to their default states.
The GPIO outputs will be selected as inputs and in high impedance.
The DIP Switch MUX_OUT and NON_MUXED_OUT pin values
depend on:
External Reset
A reset of the GPIO registers can be accomplished by holding the
I/O_OUT_LOW pin LOW for a minimum of tw. These GPIO registers
return to their default states until the I/O_OUT_LOW input is once
again HIGH.

2003 Jun 27
- the MUX_OUT_LOW and MUX_SELECT logic levels
- the previously stored values in the EEPROM register/current
Intel is a registered trademark of Intel Corporation.
8-bit I
latched 6-bit I
SEE FIGURE 2 FOR THE NEEDED COMMAND CODE.
MUX_IN pin values as shown in Table 2.
2
S
C and SMBus I/O port with 5-bit multiplexed/1-bit
1
SLAVE ADDRESS
0
0
1
2
DD
C EEPROM DIP switch and 2-kbit EEPROM
1
Figure 17. Read from GPIO Input Port Register and write to 256 byte EEPROM
, an internal power-on reset holds the
1 A0 0
DD
ACKNOWLEDGE
has reached V
FROM SLAVE
R/W
A
0
0
COMMAND BYTE
0
POR
1
. At that point,
0
0
1
ACKNOWLEDGE
FROM SLAVE
0
A
11
a7 a6 a5 a4 a3 a2 a1 a0
EEPROM ADDRESS
USING THE PCA9558 ON THE SMBus
It is possible to use Intel chipsets to communicate with the
PCA9558. There are no limitations when the SMBus Controller is
communicating with the Mux or the GPIO; however, there are
limitations with the 2K serial EEPROM. Because of being able to
address any location in the EEPROM block using the 2nd command
byte, the designer using the PCA9558 on the SMBus will have to
program around it, an easy thing to do. The device designers had to
deal with the specifics of addressing the EEPROM and chose the
I
the EEPROM block.
In order to write to the EEPROM, write the EEPROM address byte
in the Data0 byte and the data to be sent should be placed in the
Data1 byte. The Intel chipset’s Word Data instruction would then
send the address, followed by the command register then Data0
(EEPROM address), and then the Data1 (data byte). A read from
the EEPROM would be a two step process. The first step would be
to do a Write Byte with the EEPROM address in the Data0 register.
The second step would be to do a Receive Byte where the data is
stored in the command register.
Other differences from the SMBus spec:
2
C spec and use the 2nd command byte to address any location in
Paragraph 5.5.5 - Read Byte/Word in figure 5-11 - the
PCA9558 follows this same command code with one exception,
the PCA9558 requires 2 bytes of command before the repeated
start.
Paragraph 5.5.6 - Process call in figure 5-15 - the PCA9558
read operation is very similar to the SMBus process call. In the
PCA9558 read operation you send a start condition - slave
address with a write bit - 2 bytes of command code - repeated
start - slave address with a read bit - then read data.
GPIO INPUT PORT DATA LATCHED
ACKNOWLEDGE
FROM SLAVE
A
x
x
DUMMY BYTE
x
x
PROGRAMMING BEGINS AFTER STOP
x
x
ACKNOWLEDGE
FROM SLAVE
x
x
A
PCA9558
P
Product data
SW00645