pca9500 NXP Semiconductors, pca9500 Datasheet - Page 9

• Manufacturer Part Number: pca9500
• Description: 8-bit I2c And Smbus I/o Port With 2-kbit Eeprom
• Manufacturer: NXP Semiconductors

Philips Semiconductors
CHARACTERISTICS OF THE I
The I
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock phase. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (See Figure 14).
2004 Sep 30
8-bit I
2
C-bus is for 2-way, 2-line communication between different ICs
2
C and SMBus I/O port with 2-kbit EEPROM
SCL
SDA
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
SDA
SCL
START CONDITION
2
C-BUS
S
Figure 15. Definition of start and stop conditions
RECEIVER
SLAVE
Figure 16. System configuration
DATA VALID
DATA LINE
STABLE;
Figure 14. Bit transfer
TRANSMITTER/
RECEIVER
SLAVE
9
ALLOWED
CHANGE
OF DATA
Start and Stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the Start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the Stop condition (P)
(see Figure 15).
System configuration
A device generating a message is a “transmitter”, a device receiving
is the “receiver”. The device that controls the message is the
“master” and the devices which are controlled by the master are the
“slaves” (see Figure 16).
TRANSMITTER
MASTER
STOP CONDITION
P
SW00542
TRANSMITTER/
RECEIVER
MASTER
SW00543
SW00544
SDA
SCL
PCA9500
Product data sheet