pca9600 NXP Semiconductors, pca9600 Datasheet - Page 4

• Manufacturer Part Number: pca9600
• Description: Dual Bidirectional Bus Buffer
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA9600_2
Product data sheet
The logic threshold voltage levels on the I
V
current is 3 mA, the suggested maximum design sink current is 2 mA because the part
may source 1 mA.
The logic level on RX is determined from the power supply voltage V
LOW is below 40 % of V
threshold just slightly below half V
TX is an open-collector output without ESD protection diodes to V
via a pull-up resistor to a supply voltage in excess of V
exceeded. It has a larger current sinking capability than a normal I
able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down
capability as well.
A logic LOW is transmitted to TX when the voltage at I
logic LOW at RX will cause I
with I
looped back to the TX output and cause the buffer to latch LOW.
The LOW level this chip can achieve on the I
when sinking 1 mA.
If the supply voltage V
LOW. Their open-collector configuration allows them to be pulled up to the rated maximum
of 15 V even without V
loading of external signals when V
The effective input capacitance of any signal pin, measured by its effect on bus rise times,
is less than 10 pF for all bus voltages and supply voltages including V
Remark: Two or more SX or SY I/Os must not be interconnected. The PCA9600 design
does not support this configuration. Bidirectional I
direction control pin so, instead, slightly different logic LOW voltage levels are used at
SX/SY to avoid latching of this buffer. A ‘regular I
PCA9600 will be propagated to SX/SY as a ‘buffered LOW’ with a slightly higher voltage
level. If this special ‘buffered LOW’ is applied to the SX/SY of another PCA9600, that
second PCA9600 will not recognize it as a ‘regular I
to its TX/TY output. The SX/SY side of PCA9600 may not be connected to similar buffers
that rely on special logic thresholds for their operation, for example P82B96, PCA9511A,
PCA9515A, ‘B’ side of PCA9517, etc. The SX/SY side is only intended for, and compatible
with, the normal I
TX/RX signals of a second PCA9600 or P82B96 if required. The TX/RX and TY/RY I/O
pins use the standard I
restrictions on the interconnection of the TX/RX and TY/RY I/O pins to other PCA9600s,
for example in a star or multipoint configuration with the TX/RX and TY/RY I/O pins on the
common bus and the SX/SY side connected to the line card slave devices. For more
details see Application Note AN10658, “Sending I
cables” .
The PCA9600 is a direct upgrade of the P82B96 with the significant differences
summarized in
CC
. The maximum I
2
C-bus requirements (maximum 1.5 V in 5 V applications) but not low enough to be
Table
2
C-bus logic voltage levels of I
2
4.
C-bus supply voltage is 15 V, and while the guaranteed static sink
CC
CC
Rev. 02 — 13 August 2008
2
C-bus logic voltage levels of all I
CC
fails, then neither the I
present. The input configuration on SX and RX also presents no
, and logic HIGH is above 55 % of V
2
C-bus pin SX to be pulled to a logic LOW level in accordance
CC
CC
).
is not present.
2
C-bus are independent of the IC supply voltage
2
C-bus by a LOW at RX is typically 0.64 V
2
2
C-bus nor the TX output will be held
C-bus master and slave chips, or even
2
2
C-bus LOW’ applied at the RX/RY of a
2
C-bus signals do not allow any
C-bus signals via long communication
2
C-bus LOW’ and will not propagate it
CC
2
C-bus pin SX is below 0.425 V. A
2
, as long as the 15 V rating is not
C-bus parts. There are no
Dual bidirectional bus buffer
CC
CC
(with a typical switching
2
C-bus device, being
. It may be connected
CC
CC
PCA9600
© NXP B.V. 2008. All rights reserved.
of the chip. Logic
= 0 V.
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