pca9685 NXP Semiconductors, pca9685 Datasheet - Page 40

• Manufacturer Part Number: pca9685
• Description: 16-channel, 12-bit Pwm Fm+ I 2c-bus Led Controller
• Manufacturer: NXP Semiconductors

Table 14.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Symbol
t
t
t
PZH
PLH
PHL
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held LOW for a minimum of 25 ms. Disable bus
time-out feature for DC operation.
t
t
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
edge.
The maximum t
resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t
C
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
= minimum time for SDA data out to be valid following SCL LOW.
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
Dynamic characteristics
Parameter
OFF-state to HIGH propagation
delay
LOW-to-HIGH propagation delay OE to LEDn;
HIGH-to-LOW propagation delay OE to LEDn;
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t
…continued
Conditions
OE to LEDn;
OUTNE[1:0] = 10 or 11
in MODE2 register
OUTNE[1:0] = 01
in MODE2 register
OUTNE[1:0] = 00
in MODE2 register
Standard-mode
Min
-
-
-
f
I
) for the SDA output stage is specified at 250 ns. This allows series protection
2
C-bus
IL
Max
40
40
60
of the SCL signal) in order to bridge the undefined region of SCL’s falling
Fast-mode I
Min
-
-
-
2
C-bus
Max
f
40
40
60
.
Fast-mode Plus
Min
-
-
-
I
2
C-bus
Max
40
40
60
Unit
ns
ns
ns