tda9885ts NXP Semiconductors, tda9885ts Datasheet - Page 20

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tda9885ts

Manufacturer Part Number
tda9885ts
Description
I2c-bus Controlled Single And Multistandard Alignment-free If-pll Demodulators
Manufacturer
NXP Semiconductors
Datasheet

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Philips Semiconductors
9.2.4
Table 14 Bit description of SAD register for data mode (SAD = 10)
Note
1. For positive modulation choose 6.5 MHz.
Table 15 Options in extended TV mode; bit B3 = 0 of SAD 00 register
Note
1. The corresponding port function has to be disabled (set to ‘high-impedance’); see Table 11 and Chapter 12, Table
2003 Oct 02
Pin OP1
Pin OP2
Gain
I
alignment-free IF-PLL demodulators
FUNCTION
2
E1 and E0
of Characteristics, note 12.
E4 to E2
C-bus controlled single and multistandard
BIT
E7
E6
E5
D
ATA BYTE FOR DATA MODE
port function
port function
normal gain
BIT E5 = 0
VALUE
00
01
10
11
1
0
BIT E7 = 0
VIF-AGC and port features
dependent on bit E5; see Table 15
L standard PLL gating
gating in case of 36 % positive modulation
gating in case of 0 % positive modulation
VIF, SIF and tuner minimum gain
dependent on bit E7; see Table 15
Vision intermediate frequency selection
see Table 16
Sound intercarrier frequency selection (sound 2nd IF)
f
f
f
f
port function
port function
minimum gain
FM
FM
FM
FM
= 4.5 MHz
= 5.5 MHz
= 6.0 MHz
= 6.5 MHz; note 1
BIT E5 = 1
20
port function
VIF-AGC output
normal gain
DESCRIPTION
BIT E5 = 0
(1)
TDA9885; TDA9886
BIT E7 = 1
VIF-AGC external input
port function
external gain
Product specification
BIT E5 = 1
(1)

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