tda9981ahl/8/c1xx NXP Semiconductors, tda9981ahl/8/c1xx Datasheet - Page 22

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tda9981ahl/8/c1xx

Manufacturer Part Number
tda9981ahl/8/c1xx
Description
Hdmi Transmitter Up To 150 Mhz Pixel Rate With 3 ? 8-bit Video Inputs And 4 ? I 2s-bus With S/pdif
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
9. I
TDA9981A_1
Product data sheet
2
C–bus register definitions
8.15.4.1 E-EDID reading
8.15.4.2 HDCP processing
8.15.3 HDMI and DVI receiver discrimination
8.15.4 DDC channel
8.16 I
9.1 I
This information is located in the E-EDID receiver part, in the ’Vendor-Specific Datablock’
within the first CEA EDID timing extension. If the 24-bit IEEE registration identifier
contains the value 00 0C03h, then the receiver will support HDMI, otherwise the device
will be treated as a DVI device. However, the TDA9981A does not have direct access to
that information since E-EDID is read by an external microprocessor through the
TDA9981A I
The DDC-bus pins DDC_SDA and DDC_SCL are 5 V tolerant and can work at standard
mode (100 kHz).
In order to get receiver capabilities, the TDA9981A must read the E-EDID of the receiver.
This is made possible by temporarily connecting the I
microprocessor is able to read full EDID.
The DDC channel is used for the HDCP process. In this mode, the DDC channel behavior
is based on the I
The I
(400 kHz).
The registers of the TDA9981A can be accessed via the I
as a slave device and both the fast mode 400 kHz and the standard mode 100 kHz are
supported.
Bits A0 and A1 of the I
The I
Table 17.
The I
For read access, the master writes the address of the TDA9981A, the subaddress to
access the specific register and then the data.
Device address
A6
1
2
2
C-bus interface
C-bus protocol
2
2
2
C-bus pins I2C_SDA and I2C_SCL are 5 V tolerant and can work at fast mode
C-bus device address is given in
C-bus access format is shown in
A5
1
Device address
2
C-bus gate.
2
C-bus protocol and the transmitter works as a master.
A4
1
2
C-bus device address are externally selected by pins A0 and A1.
Rev. 01 — 19 May 2008
A3
0
Table
Figure
A2
0
17.
12.
150 MHz pixel rate HDMI transmitter
2
C-bus to the DDC lines, so that the
A1
A1
2
C-bus. The TDA9981A is used
TDA9981A
A0
A0
© NXP B.V. 2008. All rights reserved.
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