adv7441a Analog Devices, Inc., adv7441a Datasheet - Page 8

• Manufacturer Part Number: adv7441a
• Description: 10-bit Integrated, Multiformat Sdtv/hdtv Video Decoder, Rgb Graphics Digitizer, And 2 1 Multiplexed Hdmi/dvi Interface
• Manufacturer: Analog Devices, Inc.

ADV7441A
TIMING CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V,
CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.
Table 4.
Parameter
SYSTEM CLOCK AND CRYSTAL
I
I
RESET FEATURE
CLOCK OUTPUTS
DATA AND CONTROL OUTPUTS
I
1
2
3
4
5
6
7
2
2
2
The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (T
Guaranteed by characterization.
Refers to all I
The prefix x refers to pin names beginning with S, DDCA_S, and DDCB_S.
SDP timing figures were obtained using the default drive strength value (0x15) in User Map Register 0xF4.
CP timing figures were obtained using the maximum drive strength value (0x3F) in User Map Register 0xF4.
The suffix x refers to pin names ending with 0, 1, 2, and 3.
C PORTS (FAST MODE)
C PORTS (NORMAL MODE)
S PORT (MASTER MODE)
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC Frequency Range
xCL Frequency
xCL Minimum Pulse Width High
xCL Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
xDA Setup Time
xCL and xDA Rise Times
xCL and xDA Fall Times
Setup Time for Stop Condition
xCL Frequency
xCL Minimum Pulse Width High
xCL Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
xDA Setup Time
xCL and xDA Rise Times
xCL and xDA Fall Times
Setup Time for Stop Condition
Reset Pulse Width
LLC Mark Space Ratio
Data Output Transition Time SDR (SDP)
Data Output Transition Time SDR (CP)
SCLK Mark Space Ratio
LRCLK Data Transition Time
I2Sx Data Transition Time
MCLKOUT Frequency
1, 2
2
C pins (DDC and control port).
4
4
4
4
3
4
4
4
4
7
3
4
4
4
4
5
6
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
11
12
13
14
15
17
18
19
20
:t
:t
10
16
Test Conditions
Negative clock edge to start of valid data
End of valid data to negative clock edge
End of valid data to negative clock edge
Negative clock edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
Rev. B | Page 8 of 28
MIN
to T
MAX
).
Min
14.8
12.825
0.6
1.3
0.6
0.6
100
0.6
4
4.7
4
4.7
250
4
5
45:55
45:55
4.096
Typ
28.6363
Max
±50
110
170
400
300
300
100
1000
300
55:45
3.4
2.4
2
0.5
55:45
10
10
5
5
24.576
Unit
MHz
kHz
MHz
kHz
μs
μs
μs
μs
ns
ns
ns
μs
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ms
% duty cycle
ns
ns
ns
ns
% duty cycle
ns
ns
ppm
ns
ns
MHz