ad8432acpz Analog Devices, Inc., ad8432acpz Datasheet - Page 8

• Manufacturer Part Number: ad8432acpz
• Description: Dual Lna With Selectable Gain And Input Impedance
• Manufacturer: Analog Devices, Inc.

AD8432
THEORY OF OPERATION
LOW NOISE AMPLIFIER (LNA)
A simplified schematic of an LNA is shown in Figure 9. The
LNA is driven with a single-ended input and measured
differentially at the output. The inverting input INL must be ac-
coupled to ground for proper operation. The LNA cannot be
driven differentially due to the asymmetry of the internal gain
setting resistors. The gain from the inverting input INL to the
single-ended output (OPH or OPL) is different from the gain
from the noninverting input INH to the single-ended output.
Both inputs are capacitively coupled by the same value capacitor.
The dc input bias is 3.3 V, and dc output bias is 2.5 V. The LNA
supports a differential output voltage of 4.8 V p-p for the common-
mode output voltage of 2.5 V. Therefore, for a differential gain
G = 4, the maximum input voltage allowed is 1.2 V p-p.
The clamping technique ensures quick recovery from large
input voltages. In addition, the input back-to-back diodes, that
are integrated inside the die (IND1 and IND2), should be used
for the lowest gain configuration (12.04 dB) to protect the input
from overdriving. They should be connected after the source
resistance or before INH.
The use of fully differential topology and negative feedback
minimizes distortion. A differential signal enables smaller swings at
each output that results in reduction of third-order distortion.
Table 4. Gain Setting Using Pin-Strapping Technique and −3 dB Bandwidth for Each Gain Configuration
Differential
Gain (dB)
12.04
18.06
21.58
24.08
Single
Gain (dB)
6.02
12.04
15.56
18.06
RS
GND
VS
RG1 (Ω)
12
12
12
12
CSH
RSH
GND
CINH
RG2 (Ω)
12
12
12
12
OPH
INH
RG4
48Ω
RG3 (Ω)
Connect
GMH to GOH
24
Connect
GMH to GOH
24
Figure 9. Simplified Schematic of LNA
GOH
RG3
24Ω
RFB
Rev. PrA | Page 8 of 12
GMH
RG2
12Ω
VPS
RG4 (Ω)
Connect
GOH to OPH
Connect
GOH to OPH
48
48
Q1
I
I
The AD8432 is a voltage feedback amplifier. Due to gain
bandwidth product (GBW), a decrease in bandwidth should be
expected as the gain increases. Table 4 displays the values of −3 dB
bandwidth for each gain with unterminated input impedance.
GAIN SETTING TECHNIQUE
Pin strapping is used to set the gain of the amplifier. Gain setting
resistors are integrated in the LNA, with multiple nodes to the
resistors available externally. By externally shorting different pins,
and thereby shorting or connecting the internal resistors, the
AD8432 can be configured for several gains. The single-ended
gain from INHx to OPHx (see Figure 9) is defined as
By externally shorting the GMHx, GOHx, and OPHx pins, four
different gain configurations can be realized.
The single-ended gain from INHx to OPLx is defined as
Again, different gain configurations can be realized by
externally shorting the GMLx, GOLx, and OPLx pins.
GND
RG1
12Ω
G
G
Q2
OPH
OPL
CFB
−
I
RG5
I
−
24Ω
INH
INH
RG5 (Ω)
24
24
24
24
GML
=
=
−
RG6
24Ω
R
R
G
1
G
Preliminary Technical Data
GOL
+
5
+
RG6 (Ω)
Connect
GML to GOL
24
Connect
GML to GOL
24
R
RG7
48Ω
R
G
R
2
G
G
R
6
1
+
G
+
1
R
G
R
GND
3
G
+
7
CINL
R
OPL
INL
G
4
RG7 (Ω)
Connect
GOL to OPL
Connect
GOL to OPL
48
48
−3 dB
BW (Hz)
200 M
96 M
55 M
38 M