dac122s085eb National Semiconductor Corporation, dac122s085eb Datasheet - Page 14

• Manufacturer Part Number: dac122s085eb
• Description: 12-bit Micro Power Dual Digital-to-analog Converter With Rail-to-rail Output
• Manufacturer: National Semiconductor Corporation

www.national.com
1.0 Functional Description
1.1 DAC SECTION
The DAC122S085 is fabricated on a CMOS process with an
architecture that consists of switches and resistor strings that
are followed by an output buffer. The reference voltage is ex-
ternally applied at V
For simplicity, a single resistor string is shown in Figure 3.
This string consists of 4096 equal valued resistors with a
switch at each junction of two resistors, plus a switch to
ground. The code loaded into the DAC register determines
which switch is closed, connecting the proper node to the
amplifier. The input coding is straight binary with an ideal out-
put voltage of:
where D is the decimal equivalent of the binary code that is
loaded into the DAC register. D can take on any value be-
tween 0 and 4095. This configuration guarantees that the
DAC is monotonic.
1.2 OUTPUT AMPLIFIERS
The output amplifiers are rail-to-rail, providing an output volt-
age range of 0V to V
even rail-to-rail types, exhibit a loss of linearity as the output
approaches the supply rails (0V and V
reason, linearity is specified over less than the full output
range of the DAC. However, if the reference is less than V
there is only a loss in linearity in the lowest codes. The output
capabilities of the amplifier are described in the Electrical Ta-
bles.
The output amplifiers are capable of driving a load of 2 kΩ in
parallel with 1500 pF to ground or to V
full-scale outputs for given load currents are available in the
Electrical Characterisics Table.
1.3 RERENCE VOLTAGE
The DAC122S085 uses a single external reference that is
shared by both channels. The reference pin, V
FIGURE 3. DAC Resistor String
V
OUTA,B
REFIN
A
when the reference is V
= V
and is shared by all four DACs.
REFIN
x (D / 4096)
A
, in this case). For this
A
. The zero-code and
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A
. All amplifiers,
REFIN
, is not
A
,
14
buffered and has an input impedance of 60 kΩ. It is recom-
mended that V
output impedance. The reference voltage range is 1.0V to
V
1.4 SERIAL INTERFACE
The three-wire interface is compatible with SPI, QSPI and
MICROWIRE, as well as most DSPs and operates at clock
rates up to 40 MHz. See the Timing Diagram for information
on a write sequence.
A write sequence begins by bringing the SYNC line low. Once
SYNC is low, the data on the D
bit serial input register on the falling edges of SCLK. To avoid
misclocking data into the shift register, it is critical that
SYNC not be brought low simultaneously with a falling edge
of SCLK (see Serial Timing Diagram, Figure 2). On the 16th
falling clock edge, the last data bit is clocked in and the pro-
grammed function (a change in the DAC channel address,
mode of operation and/or register contents) is executed. At
this point the SYNC line may be kept low or brought high. Any
data and clock pusles after the 16th falling clock edge will be
ignored. In either case, SYNC must be brought high for the
minimum specified time before the next write sequence is ini-
tiated with a falling edge of SYNC.
Since the SYNC and D
are high, they should be idled low between write sequences
to minimize power consumption.
1.5 INPUT SHIFT REGISTER
The input shift register, Figure 4, has sixteen bits. The first bit
must be set to "0" and the second bit is an address bit. The
address bit determines whether the register data is for DAC
A or DAC B. This bit is followed by two bits that determine the
mode of operation (writing to a DAC register without updating
the outputs of both DACs, writing to a DAC register and up-
dating the outputs of both DACs, writing to the register of both
DACs and updating their outputs, or powering down both out-
puts). The final twelve bits of the shift register are the data
bits. The data format is straight binary (MSB first, LSB last),
with all 0's corresponding to an output of 0V and all 1's cor-
responding to a full-scale output of V
contents of the serial input register are transferred to the DAC
register on the sixteenth falling edge of SCLK. See Timing
Diagram, Figure 2.
Normally, the SYNC line is kept low for at least 16 falling
edges of SCLK and the DAC is updated on the 16th SCLK
falling edge. However, if SYNC is brought high before the 16th
falling edge, the data transfer to the shift register is aborted
and the write sequence is invalid. Under this condition, the
DAC register is not updated and there is no change in the
mode of operation or in the DAC output voltages.
A
, providing the widest possible output dynamic range.
FIGURE 4. Input Register Contents
REFIN
be driven by a voltage source with low
IN
buffers draw more current when they
IN
line is clocked into the 16-
REFIN
- 1 LSB. The
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