dac1205d750 NXP Semiconductors, dac1205d750 Datasheet - Page 13

• Manufacturer Part Number: dac1205d750
• Description: Dac1205d750 Dual 12-bit Dac, Up To 750 Msps; 4? And 8? Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
10. Application information
DAC1205D750
Product data sheet
10.2.1 Protocol description
10.1 General description
10.2 Serial peripheral interface
The DAC1205D750 is a dual 12-bit DAC which operates at up to 750 Msps. Each DAC
consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an
6-bit binary weighted sub-DAC.
The input data rate of up to 185 MHz combined with the maximum output sampling rate of
750 Msps make the DAC1205D750 extremely flexible in wide bandwidth and multi-carrier
systems. The device’s quadrature modulator and 32-bit NCO simplifies system frequency
selection. This is also possible because the 4× and 8× interpolation filters remove
undesired images.
A SYNC signal is provided to synchronize data when the PLL is in the off state.
Two modes are available for the digital input. In Dual-port mode, each DAC uses its own
data input line. In Interleaved mode, both DACs use the same data input line.
The on-chip PLL enables generation of the internal clock signals for the digital circuitry
and the DAC from a low speed clock. The PLL can be bypassed enabling the use of an
external, high-speed clock.
Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and
IOUTBP/IOUTBN. This provides a full-scale output current (I
reference is available for the reference current which is externally adjustable using pin
VIRES.
There are also some embedded features to provide an analog offset correction (auxiliary
DACs) and digital offset control as well as for gain adjustment. All the functions can be set
using the SPI.
The DAC1205D750 operates at both 3.3 V and 1.8 V each of which has separate digital
and analog power supplies. The digital input is 1.8 V and 3.3 V compliant and the clock
input is LVDS compliant.
The DAC1205D750 Serial Peripheral Interface (SPI) is a synchronous serial
communication port allowing easy interfacing with many industry microprocessors. It
provides access to the registers that define the operating modes of the chip in both write
and read modes.
This interface can be configured as a 3-wire type (SDIO as a bidirectional pin) or a 4-wire
type (SDIO and SDO as unidirectional pins, input and output port respectively). In both
configurations, SCLK acts as the serial clock and SCS_N acts as the serial chip select
bar.
Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW
assertion to drive the chip with 1 to 4 bytes, depending on the content of the instruction
byte (see
Table
All information provided in this document is subject to legal disclaimers.
7).
Rev. 2 — 10 September 2010
Dual 12-bit DAC, up to 750 Msps; 4× and 8× interpolating
DAC1205D750
O(fs)
) up to 22 mA. An internal
© NXP B.V. 2010. All rights reserved.
13 of 42