hi5905 Intersil Corporation, hi5905 Datasheet - Page 7

• Manufacturer Part Number: hi5905
• Description: 14-bit, 5 Msps A/d Converter
• Manufacturer: Intersil Corporation

Pin Descriptions
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
7
8
9
D
V
D
DV
DV
D
DV
NAME
AV
A
A
AV
V
V
V
V
ROUT
D13
D12
D11
D10
CLK
GND1
GND2
GND1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
GND
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IN
RIN
DC
IN
CC2
CC1
CC1
CC
CC
+
-
No Connection
No Connection
Digital Ground
No Connection
Analog Supply (5.0V)
Analog Ground
No Connection
No Connection
Positive Analog Input
Negative Analog Input
DC Bias Voltage Output
No Connection
Reference Voltage Output
Reference Voltage Input
Analog Ground
Analog Supply (5.0V)
No Connection
Data Bit 11 Output (MSB)
Data Bit 11 Output
Data Bit 11 Output
Data Bit 10 Output
No Connection
No Connection
Data Bit 9 Output
Data Bit 8 Output
Digital Ground
Digital Supply (5.0V)
No Connection
Data Bit 7 Output
Data Bit 6 Output
Data Bit 5 Output
Data Bit 4 Output
Data Bit 3 Output
No Connection
No Connection
Data Bit 2 Output
Data Bit 1 Output
Data Bit 0 Output (LSB)
No Connection
Input Clock
Digital Supply (5.0V)
Digital Ground
Digital Supply (5.0V)
No Connection
19
DESCRIPTION
HI5905
Detailed Description
Theory of Operation
The HI5905 is a 14-bit fully differential sampling pipeline A/D
converter with digital error correction. Figure 8 depicts the
circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
clock which is a non-overlapping two phase signal,
phase,
tors, C
discharged to analog ground. At the falling edge of
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase,
plates of the sampling capacitors are connected together
and the holding capacitors are switched to the op-amp out-
put nodes. The charge then redistributes between C
C
fully-differential, sampled-data representation of the analog
input. The circuit not only performs the sample-and-hold
function but will also convert a single-ended input to a fully-
differential output for the converter core. During the sampling
phase, the V
and C
result in a typical full power input bandwidth of 100MHz for
the converter.
As illustrated in the functional block diagram and the timing
diagram in Figure 1, four identical pipeline subconverter stages,
each containing a four-bit flash converter, a four-bit digital-to-
analog converter and an amplifier with a voltage gain of 8,
follow the S/H circuit with the fifth stage being only a 4-bit flash
converter. Each converter stage in the pipeline will be sampling
in one phase and amplifying in the other clock phase. Each
individual sub-converter clock signal is offset by 180 degrees
from the previous stage clock signal, with the result that
alternate stages in the pipeline will perform the same operation.
The output of each of the four-bit subconverter stages is a
four-bit digital word containing a supplementary bit to be used
by the digital error correction logic. The output of each sub-
converter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the four
identical four-bit subconverter stages with the corresponding
output of the fifth stage flash converter before applying the
twenty bit result to the digital error correction logic. The digital
error correction logic uses the supplementary bits to correct
any error that may exist before generating the final fourteen bit
digital data output of the converter.
2
H
, derived from the master clock. During the sampling
completing one sample-and-hold cycle. The output is a
S
V
S
FIGURE 8. ANALOG INPUT SAMPLE-AND-HOLD
V
IN
. The relatively small values of these components
. At the same time the holding capacitors, C
IN
1
+
, the input signal is applied to the sampling capaci-
-
IN
1
1
2
pins see only the on-resistance of a switch
C
C
S
S
1
1
-
+
+
C
-
C
H
H
2
1
, the two bottom
1
V
V
OUT
OUT
+
-
H
S
1
1
, are
and
and
the