adsp-21371 Analog Devices, Inc., adsp-21371 Datasheet - Page 14

• Manufacturer Part Number: adsp-21371
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21371
DATA MODES
The upper 32 data pins of the external memory interface are
muxed (using bits in the SYSCTL register) to support the exter-
nal memory interface data (input/output), the PDAP (input
only), and the FLAGS (input/output).
settings.
Table 6. Function of Data Pins
1
BOOT MODES
Table 7. Boot Mode Selection
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
For details on processor timing, see
Figure 3 on Page
Table 8. Core Instruction Rate/ CLKIN Ratio Selection
DATA PIN MODE
000
001
010
011
100
101
110
111
BOOTCFG1–0
00
01
10
CLKCFG1–0
00
01
10
These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control signals
FLAGS/PWM_SEL. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21367/8/9 Processors.
17.
Booting Mode
SPI Slave Boot
SPI Master Boot
EPROM/FLASH Boot
Core to CLKIN Ratio
6:1
32:1
16:1
Timing Specifications
Table 6
FLAGS/PWM15–0
FLAGS/PWM15–0
FLAGS/PWM15–0
DATA31–16
provides the pin
PDAP (DATA + CTRL)
PDAP (DATA + CTRL)
Rev. 0 | Page 14 of 48 | June 2007
1
1
1
and
Three-state all pins
EPDATA32–0
Reserved
FLAGS15–8
DATA15–8
EPDATA15–0
FLAGS15–0
EPDATA7–0
EPDATA7–0
FLAGS7–0
DATA7–0