adsp-21371 Analog Devices, Inc., adsp-21371 Datasheet - Page 27

• Manufacturer Part Number: adsp-21371
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Memory Read
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 25. Memory Read
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) x t
IC = (number of idle cycles specified in AMICTLx register) x t
H = (number of hold cycles specified in AMICTLx register) x t
Data delay/setup: System must meet t
The falling edge of MSx, is referenced.
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
Data hold: User must meet t
ACK delay/setup: User must meet t
DAD
DRLD
SDS
HDRH
DAAK
DSAK
DRHA
DARL
RW
RWR
ADDRESS
MSx
DATA
ACK
WR
RD
—
Address, Selects Delay to Data Valid
RD Low to Data Valid
Data Setup to RD High
Data Hold from RD High
ACK Delay from Address, Selects
ACK Delay from RD Low
Address Selects Hold After RD High
Address Selects to RD Low
RD Pulse Width
RD High to WR, RD, Low
Bus Master
HDRH
—
Bus Master
in asynchronous access mode. See
DAAK
DAD
t
DARL
, or t
t
, t
DAAK
DRLD
DSAK
1
, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t
, or t
4
3, 4
SDS.
2
t
DSAK
t
DAD
2, 5
Figure 17. Memory Read—Bus Master
Rev. 0 | Page 27 of 48 | June 2007
1, 2
t
DRLD
Test Conditions on Page 44
SDCLK
SDCLK
SDCLK
).
.
.
t
Min
2.2
0
RHC + 0.38
t
W – 1.4
HI + t
RW
SDCLK
SDCLK
–3.3
–0.8
for the calculation of hold times given capacitive and dc loads.
t
SDS
SDCLK
W+t
W – 3
t
Max
W – 7.0
SDCLK
SDCLK
–10.1+ W
t
t
HDRH
DRHA
t
RWR
–5.12
DAAK
or t
ADSP-21371
DSAK
.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns