adsp-21371kswz-2a Analog Devices, Inc., adsp-21371kswz-2a Datasheet - Page 29

• Manufacturer Part Number: adsp-21371kswz-2a
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 27. Memory Read—Bus Master
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) × t
IC = (number of idle cycles specified in AMICTLx register) × t
H = (number of hold cycles specified in AMICTLx register) × t
Data delay/setup: System must meet t
The falling edge of MSx, is referenced.
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
Data hold: User must meet t
ACK delay/setup: User must meet t
DAD
DRLD
SDS
HDRH
DAAK
DSAK
DRHA
DARL
RW
RWR
capacitive and dc loads.
t
DAAK
ADDRESS
MSx
or t
DATA
ACK
WR
DSAK
RD
.
Address, Selects Delay to Data Valid
RD Low to Data Valid
Data Setup to RD High
Data Hold from RD High
ACK Delay from Address, Selects
ACK Delay from RD Low
Address Selects Hold After RD High
Address Selects to RD Low
RD Pulse Width
RD High to WR, RD, Low
HDRH
in asynchronous access mode. See
DAAK
DAD
t
DARL
, or t
t
, t
DAAK
DRLD
DSAK
1
, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet
, or t
4
3, 4
SDS.
2
t
DSAK
t
DAD
2, 5
Figure 17. Memory Read—Bus Master
Rev. B | Page 29 of 52 | June 2008
1, 2
t
DRLD
Test Conditions on Page 46
SDCLK
SDCLK
SDCLK
)
1.2 V, 266 MHz
Min
2.2
0
RHC + 0.38
t
W – 1.4
HI + t
t
SDCLK
RW
SDCLK
– 3.3
– 0.8
for the calculation of hold times given
t
SDS
SDCLK
Max
W + t
W – 3
t
W – 7.0
SCDCLK
SDCLK
– 10. + W
– 5.12
ADSP-21371/ADSP-21375
t
t
HDRH
DRHA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RWR