adsp-21mod870-100 Analog Devices, Inc., adsp-21mod870-100 Datasheet - Page 19

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adsp-21mod870-100

Manufacturer Part Number
adsp-21mod870-100
Description
Internet Gateway Processor
Manufacturer
Analog Devices, Inc.
Datasheet
TIMING PARAMETERS
Parameter
Clock Signals and Reset
Timing Requirements:
t
t
t
Switching Characteristics:
t
t
t
Control Signals
Timing Requirements:
t
t
t
NOTE
1
REV. 0
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
CKI
CKIL
CKIH
CKL
CKH
CKOH
RSP
MS
MH
oscillator start-up time).
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
RESET Width Low
Mode Setup before RESET High
Mode Setup after RESET High
CLKOUT
PF(3:0)
RESET
CLKIN
*
*
PF3 IS MODE D
,
PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
Figure 21. Clock Signals
t
t
RSP
CKIL
t
CKI
t
MS
t
CKL
–19–
t
MH
t
CKOH
t
CKH
Min
38
15
15
0.5 t
0.5 t
0
5 t
2
5
t
CK
CKIH
CK
CK
1
– 7
– 7
ADSP-21mod870
Max
100
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

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