adsp-21mod870-100 Analog Devices, Inc., adsp-21mod870-100 Datasheet - Page 6

• Manufacturer Part Number: adsp-21mod870-100
• Description: Internet Gateway Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21mod870
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-21mod870 provides four dedicated external inter-
rupt input pins, IRQ2, IRQL0, IRQL1, and IRQE (shared with
the PF7:4 pins). In addition, SPORT1 may be reconfigured for
IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six
external interrupts. The ADSP-21mod870 also supports internal
interrupts from the timer, the byte DMA port, the two serial
ports, software and the power-down control circuit. The inter-
rupt levels are internally prioritized and individually maskable
(except power down and reset). The IRQ2, IRQ0 and IRQ1
input pins can be programmed to be either level- or edge-
sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is
edge-sensitive. The priorities and vector addresses of all inter-
rupts are shown in Table I.
Source of Interrupt
Reset (or Power-Up with
Power-Down (Nonmaskable) 002C
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or IRQ1 0020
SPORT1 Receive or IRQ0
Timer
Interrupt routines can either be nested with higher priority inter-
rupts taking precedence or processed sequentially. Interrupts can
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
power-down interrupt is nonmaskable.
The ADSP-21mod870 masks all interrupts for one instruction
cycle following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering or
DMA transfers.
The interrupt control register, ICNTL, controls interrupt nesting
and defines the IRQ0, IRQ1 and IRQ2 external interrupts to be
either edge- or level-sensitive. The IRQE pin is an external edge
sensitive interrupt and can be forced and cleared. The IRQL0
and IRQL1 pins are external level-sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are twelve levels deep to allow interrupt, loop, and subroutine
nesting. The following instructions allow global enable or disable
servicing of the interrupts (including power down), regardless of
the state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
Table I. Interrupt Priority and Interrupt Vector Addresses
PUCR = 1)
Interrupt Vector Address (Hex)
0000 (Highest Priority)
0004
0008
000C
0010
0014
0018
001C
0024
0028 (Lowest Priority)
–6–
LOW POWER OPERATION
The ADSP-21mod870 has three low power modes that signifi-
cantly reduce the power dissipation when the device operates
under standby conditions. These modes are:
• Power-Down
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
The ADSP-21mod870 Internet gateway processor has a low
power feature that lets the processor enter a very low power
dormant state through hardware or software control. Here is a
brief list of power-down features. Refer to the ADSP-2100 Fam-
ily User’s Manual, Third Edition, “System Interface” chapter, for
detailed information about the power-down feature.
• Quick recovery from power-down. The processor begins
• Support for an externally generated TTL or CMOS processor
• Support for crystal operation includes disabling the oscillator
• Power-down is initiated by either the power-down pin (PWD)
• Context clear/save control allows the processor to continue
• The RESET pin also can be used to terminate power-down.
• Power-down acknowledge pin indicates when the processor
Idle
When the ADSP-21mod870 is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruc-
tion. In Idle Mode IDMA, BDMA and autobuffer cycle steals
still occur.
Slow Idle
The IDLE instruction is enhanced on the ADSP-21mod870 to
let the processor’s internal clock signal be slowed, further reduc-
ing power consumption. The reduced clock frequency, a pro-
grammable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction.
The format of the instruction is
IDLE (n);
where n = 16, 32, 64 or 128. This instruction keeps the processor
fully functional, but operating at the slower clock rate. While it is
in this state, the processor’s other internal clock signals, such as
SCLK, CLKOUT and timer clock, are reduced by the same
executing instructions in as few as 400 CLKIN cycles.
clock. The external clock can continue running during power-
down without affecting the lowest power rating and 400 CLKIN
cycle recovery.
to save power (the processor automatically waits approxi-
mately 4096 CLKIN cycles for the crystal oscillator to start or
stabilize), and letting the oscillator run to allow 400 CLKIN
cycle startup.
or the software power-down force bit. Interrupt support al-
lows an unlimited number of instructions to be executed
before optionally powering down. The power-down interrupt
also can be used as a nonmaskable, edge-sensitive interrupt.
where it left off or start with a clean context when leaving the
power-down state.
has entered power-down.
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