saa7182a NXP Semiconductors, saa7182a Datasheet - Page 37

• Manufacturer Part Number: saa7182a
• Description: Digital Video Encoder Euro-denc2
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1996 Oct 02
handbook, full pagewidth
handbook, full pagewidth
Digital Video Encoder (EURO-DENC2)
The data demultiplexing phase is coupled to the internal horizontal phase.
The CREF signal applies only for the 16 line digital TV format, because these signals are only valid in 13.5 MHz.
The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S).
(1) Sequence bit:
(2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems.
(3) Only from SAA7111 decoder.
(4) SAAA7111 provides (22 : 0) bits, resulting in 3 reserved bits before sequence bit.
RTCI
PAL = logic 0 then (R
NTSC = logic 0 then no change.
LLC
CREF
MP(n)
DP(n)
RCV2
H/L transition
count start
128
time slot:
Y) line normal; PAL = logic 1 then (R
LOW
0 1
Cb(0)
13
Y(0)
SAA7182A/83A
increment
not used in
HPLL
14
0
Fig.17 Digital TV timing.
reserved
Cr(0)
4 bits
Y(1)
Fig.18 RTCI timing.
19
21
Y) line inverted.
37
Cb(2)
Y(2)
FSCPLL increment (4)
sample
valid
sample
invalid
SAA7182A; SAA7183A
Cr(2)
Y(3)
reserved
8/LLC
5 bits
Preliminary specification
sequence
0
bit (1)
Cb(4)
Y(4)
MBE739
67 68
bit (3)
reset
reserved (2)
MGD673