saa7105e NXP Semiconductors, saa7105e Datasheet - Page 3

• Manufacturer Part Number: saa7105e
• Description: Digital Video Encoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1
2004 Mar 04
Digital PAL/NTSC encoder with integrated high quality
scaler and anti-flicker filter for TV output from a PC
Supports Intel
interfacing to graphics controller
27 MHz crystal-stable subcarrier generation
Maximum graphics pixel clock 85 MHz at double edged
clocking, synthesized on-chip or from external source
Programmable assignment of clock edge to bytes (in
double edged mode)
Synthesizable pixel clock (PIXCLK) with minimized
output jitter, can be used as reference clock for the VGC,
as well)
PIXCLK output and bi-phase PIXCLK input (VGC clock
loop-through possible)
Hot-plug detection through dedicated interrupt pin
Supported VGA resolutions for PAL or NTSC legacy
video output up to 1280
60 or 50 Hz frame rate
Supported VGA resolutions for HDTV output up to
1920
frame rate
Three Digital-to-Analog Converters (DACs) for CVBS
(BLUE, C
27 MHz sample rate (signals in parenthesis are
optionally), all at 10-bit resolution
Non-interlaced C
4 : 4 : 4 sampling
Downscaling and upscaling from 50 to 400%
Optional interlaced C
Disk (DVD) signals
Optional non-interlaced RGB output to drive second
VGA monitor (bypass mode, maximum 85 MHz)
3
Support for hardware cursor
HDTV up to 1920
progressive, including 3-level sync pulses
Digital video encoder
FEATURES
256 bytes RGB Look-Up Table (LUT)
1080 interlaced graphics data at 60 or 50 Hz
B
), VBS (GREEN, CVBS) and C (RED, C
Digital Video Out (DVO) low voltage
B
-Y-C
1080 interlaced and 1280
B
-Y-C
R
or RGB input at maximum
1024 graphics data at
R
input of Digital Versatile
720
R
) at
3
(1) Macrovision
Programmable border colour of underscan area
Programmable 5 line anti-flicker filter
On-chip 27 MHz crystal oscillator (3rd-harmonic or
fundamental 27 MHz crystal)
Fast I
Encoder can be master or slave
Adjustable output levels for the DACs
Programmable horizontal and vertical input
synchronization phase
Programmable horizontal sync output phase
Internal Colour Bar Generator (CBG)
Optional support of various Vertical Blanking Interval
(VBI) data insertion
Macrovision
rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; this
applies to the SAA7104E only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited. Please
contact your nearest Philips Semiconductors sales
office for more information.
Optional cross-colour reduction for PAL and NTSC
CVBS outputs
Power-save modes
Joint Test Action Group (JTAG) boundary scan test
Monolithic CMOS 3.3 V device, 5 V tolerant I/Os.
2
C-bus control port (400 kHz)
(1)
is a trademark of the Macrovision Corporation.
Pay-per-View copy protection system
SAA7104E; SAA7105E
Product specification