saa7715h NXP Semiconductors, saa7715h Datasheet
saa7715h
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... DATA SHEET SAA7715H Digital Signal Processor Preliminary specification File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 2001 May 07 ...
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... C-BUS TIMING 16 APPLICATION DIAGRAM 17 PACKAGE OUTLINE 18 SOLDERING 18.1 Introduction to soldering surface mount packages 18.2 Reflow soldering 18.3 Wave soldering 18.4 Manual soldering 18.5 Suitability of surface mount IC packages for wave and reflow soldering methods 19 DATA SHEET STATUS 20 DEFINITIONS 21 DISCLAIMERS 22 PURCHASE OF PHILIPS I 2 Preliminary specification SAA7715H 2 C COMPONENTS ...
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... Multichannel decoding: Dolby Pro Logic and virtual 3D surround PC/USB audio applications: stereo widening (Incredible surround), sound steering, sound positioning and speaker equalization. 3 Preliminary specification SAA7715H ...
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... DSPFREQ frequency pin POWERDOWN enabled at IIS_WS1, SPDIF1 or SPDIF2 input code = 0 DIV_CLK_IN = LOW DIV_CLK_IN = HIGH PACKAGE DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body Preliminary specification SAA7715H MIN. TYP. MAX. UNIT 3.15 3.3 3. 380 mW 400 ...
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... Acrobat reader. white to force landscape pages to be ... handbook, full pagewidth IIS_BCK1 2 IIS_WS1 3 IIS_IN1 5 IIS_IN4 SAA7715H 6 IIS_IN2 9 IIS_IN3 2 S PLL XRAM YRAM ...
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... FSDAC positive supply voltage (bond out to 2 pads) analog right output pin FSDAC ground supply voltage (bond out to 2 pads) voltage reference pin of FSDAC power-on mute pin of FSDAC standby mode of chip 6 Preliminary specification SAA7715H ...
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... CLK_IN by two digital input/output flag of the DSP-core (F5 of the status register) digital input/output flag of the DSP-core (F6 of the status register) digital input/output flag of the DSP-core (F7 of the status register) EXPLANATION 2 C-bus specification tolerant 7 Preliminary specification SAA7715H ...
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... IIS_BCK1 IIS_WS1 IIS_IN1 RESERVED1 IIS_IN4 IIS_IN2 RESERVED2 RESERVED3 IIS_IN3 V SSI2 A0 2001 May SAA7715H Fig.2 Pin configuration. 8 Preliminary specification SAA7715H 33 IIS_BCK 32 IIS_WS 31 IIS_OUT1 30 IIS_OUT2 29 IIS_OUT3 28 IIS_OUT4 27 SYSCLK TSCAN 26 25 SPDIF1 24 SPDIF2 V DDE 23 MGT827 ...
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... SYSCLK (n 0 512 1 384 0 256 1 192 0 128 9 Preliminary specification SAA7715H 2 C-bus (see Table 10). DSP_TURBO DIV_CLK_IN clock. The memory map of the I s sel_loop_div[1:0] ...
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... The flags can be used by the DSP depending on the downloaded software. 10 Preliminary specification P OWER OFF PLOP SUPPRESSION P VREFDA IN FOR INTERNAL REFERENCE S UPPLY OF THE ANALOG OUTPUTS and V DDA1 must have sufficient decoupling to prevent THD External control pins SAA7715H is DDA1 . SSA1 . The SSA1 ...
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... The design fulfils the digital audio interface specification “IEC 60958-1 Ed2, part 1, general part IEC 60958-3 Ed2, part 3, consumer applications” C-bus bit): 11 Preliminary specification SAA7715H SPDIF INPUTS C-bus, the microprocessor controller can decide to 2 C-bus registers 2 C-bus or by the ...
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Acrobat reader. white to force landscape pages to be ... WS LEFT BCK DATA MSB B2 MSB INPUT ...
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... Figure 4 shows the time the chip actually is in Power-down mode after switching on/off pin POWERDOWN 128 (256/CLK_IN); 8.192 MHz < CLK_IN < 12.288 MHz 128 (512/CLK_IN); 16.384 MHz < CLK_IN < 24.576 MHz. B Fig.4 Power-down mode. 13 Preliminary specification SAA7715H 2 C-bus bits to their default value and it 2 C-bus during t B MGT828 ...
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... C-bus register at execution of the MPI instruction in the DSP program. Therefore at least once every DSP routine an MPI instruction should be added. LSB R/W 14 Preliminary specification 2 C-bus memory map, see 2 C-bus interface. The Read cycles 2 C-bus configuration for a read cycle is shown SAA7715H 2 C-bus and the ...
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Acrobat reader. white to force landscape pages to be ... ADDR ...
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... DATA WORD MBBB BBBB BBBB BBBB BBBB BBBB BBBB BBBL MBBB BBBB BBBB BBBB BBBB BBBL MBBB BBBB BBBB BBBB BBBB BBBL MBBB BBBB BBBB BBBB BBBB BBBL XXXX MBBB BBBB BBBL 16 Preliminary specification SAA7715H 2 C-bus to a BYTES (NUMBER ...
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... DSP to XRAM DESCRIPTION Selector register 1 SPDIF IN channel status register 1 left SPDIF IN channel status register 2 left SPDIF IN channel status register 1 right SPDIF IN channel status register 2 right DSP and general control register 17 Preliminary specification SAA7715H SIZE 2k 32 bits 1 24 bits 1.5k 32 bits 512 12 bits ...
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... DESCRIPTION channel status SPDIF in right LSB bits DESCRIPTION channel status SPDIF in right MSB bits Preliminary specification SAA7715H BIT DEFAULT POSITION 0 0 00011 ...
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... SPDIF2 or digital serial input 3 1: SPDIF2 0: digital serial input 3 select channel status information taken from SPDIF1 or SPDIF2 1: from input SPDIF2 0: from input SPDIF1 reserved 19 Preliminary specification SAA7715H BIT DEFAULT POSITION 00000H BIT DEFAULT POSITION 00000H ...
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... Preliminary specification 0050C6H 0010DBH 000000H 000000H 000000H 000000H OUTPUT 2 standard I S-bus LSB-justified, 16 bits LSB-justified, 18 bits LSB-justified, 20 bits LSB-justified, 24 bits OUTPUT 2 standard I S-bus LSB-justified, 16 bits LSB-justified, 18 bits LSB-justified, 20 bits LSB-justified, 24 bits SAA7715H ...
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... Compression ratio is changed by selecting one of the values in the drop-down list labelled ‘Ratio’. To increase the amount of compression, select one of the higher ratios. For a more subtle effect, select a lower setting, such as input level (dB) 1.5:1. MGT830 21 Preliminary specification SAA7715H Control parameters Fixed versus variable mode Threshold Ratio ...
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... More specifically, for each band, users can control the band’s centre frequency, and also the width of the band of frequencies that are affected. 22 Preliminary specification SAA7715H ...
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... INTS AND TIPS Try a mix setting of about 0 starting point. For best results, position yourself between the speakers and a couple of feet back. Ideally, your ears should be at about the same level as the speakers, but this is not so critical. 23 Preliminary specification SAA7715H ...
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... CIC specification/test method PARAMETER mounted on printed-circuit board 24 Preliminary specification CONDITIONS MIN. 0.5 0.5 > 0 > 0 < 0 200 2000 100 CONDITIONS VALUE 60 SAA7715H MAX. UNIT +3 +85 C +125 600 mW UNIT K/W ...
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... V; unless otherwise specified DD standard output slew rate output slew rate output slew rate output Preliminary specification SAA7715H MIN. TYP. MAX. 3.15 3.3 3. 6.5 13 250 13.5 27 380 400 2.0 0.8 ...
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... slew rate output slew rate output C-bus output 400 3.3 V; unless otherwise specified amb DDA2 at 1 kHz 26 Preliminary specification SAA7715H MIN. TYP. MAX. 0.4 0.4 0.4 0.4 0 140 30 50 100 3.5 6 200 3 ...
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... CONDITIONS = 44.1 kHz all voltages referenced to ground; s amb L pins 34 and 36 (THD + N)/S < 0. pin code = kHz; ripple ripple(p-p) 27 Preliminary specification SAA7715H MIN. TYP. MAX. 0.13 3.0 0.22 3 200 28 1000 0 100 80 50 UNIT ...
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... CONDITIONS Preliminary specification SAA7715H LEFT t su(WS) t su(D) t h(D) MSB MSB MIN. TYP. MAX. 162 0.15T 0.15T 0.35T cy 0.35T cy 0.2T cy 0.2T cy 0.15T 0.2T cy 0.2T cy MGM129 UNIT ns ns ...
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... SU;DAT t SU;STA t HIGH Sr Fig.10 Definition of timing on the I STANDARD MODE CONDITIONS MIN. 0 4.7 4.0 4.7 4.0 4.7 0 250 4.0 not applicable 29 Preliminary specification SAA7715H t HD;STA SU;STO P 2 C-bus. 2 FAST MODE I C-BUS 2 I C-BUS MAX. MIN. MAX. 100 0 400 1.3 0.6 1.3 0.6 0.6 0 0.9 100 1000 ...
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... Acrobat reader. white to force landscape pages to be ... SPDIF input signals 75 75 100 nF 100 nF 100 pF 100 IIS_BCK1 1 IIS_WS1 2 IIS_IN1 3 IIS_IN4 5 digital SAA7715H inputs IIS_IN2 6 IIS_IN3 DSP CLOCK PLL 22 41 (1) Omit this capacitor when a microcontroller is used. 100 100 100 ...
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... 2.5 scale (1) ( 0.40 0.25 10.1 10.1 12.9 0.8 0.20 0.14 9.9 9.9 12.3 REFERENCES JEDEC EIAJ 31 Preliminary specification detail 12.9 0.95 1.3 0.15 0.15 0.1 12.3 0.55 EUROPEAN PROJECTION SAA7715H SOT307 (1) ( 1.2 1 0.8 0.8 0 ISSUE DATE 95-02-04 97-08-01 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 32 Preliminary specification SAA7715H ...
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... This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. 33 Preliminary specification SAA7715H SOLDERING METHOD WAVE REFLOW suitable (2) suitable ...
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... C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 34 Preliminary specification SAA7715H These products are not Philips Semiconductors 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors Digital Signal Processor 2001 May 07 NOTES 35 Preliminary specification SAA7715H ...
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Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + 101 ...