ep2c35 Altera Corporation, ep2c35 Datasheet - Page 34

• Manufacturer Part Number: ep2c35
• Description: Cyclone Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Global Clock Network & Phase-Locked Loops
Figure 2–13. Clock Control Block
Notes to
(1)
(2)
(3)
(4)
2–22
Cyclone II Device Handbook, Volume 1
CLK[n + 3]
CLK[n + 2]
CLK[n + 1]
CLK[n]
The CLKSWITCH signal can either be set through the configuration file or it can be dynamically set when using the
manual PLL switchover feature. The output of the multiplexer is the input reference clock (f
The CLKSELECT[1..0] signals are fed by internal logic and can be used to dynamically select the clock source for
the global clock network when the device is in user mode.
The static clock select signals are set in the configuration file and cannot be dynamically controlled when the device
is in user mode.
Internal logic can be used to enabled or disabled the global clock network in user mode.
Figure
2–13:
inclk1
inclk0
Static Clock Select (3)
CLKSWITCH (1)
Of the sources listed, only two clock pins, two PLL clock outputs, one
DPCLK pin, and one internally-generated signal are chosen to drive into a
clock control block.
clock control block. Out of these six inputs, the two clock input pins and
two PLL outputs can be dynamic selected to feed a global clock network.
The clock control block supports static selection of DPCLK and the signal
from internal logic.
f
IN
PLL
Internal Logic
DPCLK or
CDPCLK
C0
C1
C2
Figure 2–13
(3)
CLKSELECT[1..0] (2)
shows a more detailed diagram of the
Clock Control Block
Static Clock
Select (3)
CLKENA (4)
IN
Enable/
Disable
Altera Corporation
) for the PLL.
February 2007
Global
Clock