ep2c35 Altera Corporation, ep2c35 Datasheet - Page 55

• Manufacturer Part Number: ep2c35
• Description: Cyclone Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 2–25. Cyclone II IOE in Bidirectional I/O Configuration
Altera Corporation
February 2007
Interconect
Column
or Row
io_clk[5..0]
data_in1
data_in0
Chip-Wide Reset
OE
clkout
aclr/prn
ce_in
ce_out
clkin
sclr/preset
The Cyclone II device IOE includes programmable delays to ensure zero
hold times, minimize setup times, or increase clock to output times.
A path in which a pin directly drives a register may require a
programmable delay to ensure zero hold time, whereas a path in which a
pin drives a register through combinational logic may not require the
delay. Programmable delays decrease input-pin-to-logic-array and IOE
input register delays. The Quartus II Compiler can program these delays
to automatically minimize setup time while providing a zero hold time.
Output Register
Input Register
OE Register
D
D
D
CLRN
CLRN
CLRN
PRN
ENA
PRN
ENA
PRN
ENA
Q
Q
Q
Pin Delay
Open-Drain Output
Output
Cyclone II Device Handbook, Volume 1
Input Register Delay
Logic Array Delay
or Input Pin to
Input Pin to
Cyclone II Architecture
V
CCIO
V
CCIO
Optional
PCI Clamp
Programmable
Pull-Up
Resistor
Bus Hold
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