at60142et-dd20sms ATMEL Corporation, at60142et-dd20sms Datasheet - Page 10

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at60142et-dd20sms

Manufacturer Part Number
at60142et-dd20sms
Description
Rad Hard 512k X 8 Very Low Power Cmos Sram
Manufacturer
ATMEL Corporation
Datasheet
Figure 3. Write Cycle 1. WE Controlled, OE High During Write
Figure 4. Write Cycle 2. WE Controlled, OE Low
Figure 5. Write Cycle 3. CS Controlled
Note:
4156F–AERO–06/04
The internal write time of the memory is defined by the overlap of CS Low and W LOW. Both signals must be activated to initiate
a write and either signal can terminate a write by going in active mode. The data input setup and hold timing should be refer-
enced to the active edge of the signal that terminates the write.
Data out is high impedance if OE= V
E
E
E
(1)
IH
.
AT60142E/ET
10

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