at94k40al ATMEL Corporation, at94k40al Datasheet - Page 174

• Manufacturer Part Number: at94k40al
• Description: At94kal Series Field Programmable System Level Integrated Circuit
• Manufacturer: ATMEL Corporation

6.1.1
Table 6-2.
Table 6-3.
174
Symbol
t
t
t
t
t
t
t
Symbol
t
t
t
t
t
t
ADS
ADH
RDS
RDH
ACC
MEH
MEl
ADS
ADH
WRS
MPW
WDS
WDH
AT94KAL Series FPSLIC
Frame Interface
Parameter
Address Setup
Address Hold
Read Cycle Setup
Read Cycle Hold
Access Time from Posedge ME
Minimum ME High
Minimum ME Low
Parameter
Address Setup
Address Hold
Write Cycle Setup
Minimum Write Duration
Data Setup to Write End
Data Hold to Write End
SRAM Read Cycle Timing Numbers
Commercial 3.3V ± 10%/Industrial 3.3V ± 10%
SRAM Write Cycle Timing Numbers
Commercial 3.3V ± 10%/Industrial 3.3V ± 10%
The FPGA Frame Clock phase is selectable (see
page
relation of ME to data, address and write enable does not change). By default, FrameClock is
inverted (ME = ~FrameClock). Selecting the non-inverted phase assigns ME = FrameClock.
Recall, the Dual-port SRAM operates in single-edge clock controlled mode during read opera-
tions, and double-edge clock controlled mode during writes. Addresses are clocked internally on
the rising edge of the clock signal (ME). Any change of address without a rising edge of ME is
not considered.
30). This document refers to the clock at the FPGA/Dual-port SRAM interface as ME (the
Minimum
Minimum
0.6
0.7
3.4
0.7
0.6
0.6
0.7
1.4
4.6
0.6
0
0
0
Commercial
Commercial
Typical
Typical
0.8
0.9
4.2
0.9
0.8
0.8
0.9
1.8
5.7
0.8
0
0
0
Maximum
Maximum
1.1
1.3
5.9
1.1
1.3
8.0
1.3
1.1
2.5
1.1
0
0
0
“System Control Register – FPGA/AVR” on
Minimum
Minimum
0.5
0.6
2.9
0.6
0.6
0.5
0.6
1.2
3.9
0.5
0
0
0
Industrial
Industrial
Typical
Typical
0.8
0.9
4.2
0.9
0.8
0.8
0.9
1.8
5.7
0.8
0
0
0
Maximum
Maximum
1.2
1.5
6.9
1.5
1.2
1.5
3.0
1.3
9.4
1.3
0
0
0
1138I–FPSLI–1/08
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns