cy8c5246pvi-092 Cypress Semiconductor Corporation., cy8c5246pvi-092 Datasheet - Page 26

• Manufacturer Part Number: cy8c5246pvi-092
• Description: Programmable System-on-chip Psoc
• Manufacturer: Cypress Semiconductor Corporation.

Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High
Voltage Interrupt
Document Number: 001-55034 Rev. *A
Interrupt Supply
PRES - Precise Low Voltage Reset
This circuit monitors the outputs of the analog and digital inter-
nal regulators after power up. The regulator outputs are com-
pared to a precise reference voltage of 1.6V ±0.02V. The re-
sponse to a PRES trip is identical to an IPOR reset.
In normal operating mode, the program cannot disable the dig-
ital PRES circuit. The analog regulator can be disabled, which
also disables the analog portion of the PRES. The PRES cir-
cuit is disabled automatically during sleep and hibernate
modes, with one exception: During sleep mode the regulators
are periodically activated (buzzed) to provide supervisory ser-
vices and to reduce wakeup time. At these times the PRES
circuit is also buzzed to allow periodic voltage monitoring.
HRES - Hibernate/Sleep Low Voltage Reset
This circuit monitors internal voltage and issues a reset if the
voltage drops below a point where state information may be
lost. The response to a HRES trip is identical to an IPOR reset.
This circuit is ultra low power. It is enabled at all times but its
output only causes a reset when the device is in hibernate or
sleep mode.
ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog
High Voltage Interrupt
Interrupt circuits are available to detect when Vdda and Vddd
go outside a voltage range. For AHVI, Vdda is compared to a
fixed trip level. For ALVI and DLVI, Vdda and Vddd are com-
pared to trip levels that are programmable, as listed in
Table
The monitors are disabled until after IPOR. During sleep mode
these circuits are periodically activated (buzzed). If an interrupt
occurs during buzzing then the system first enters its wakeup
sequence. The interrupt is then recognized and may be ser-
viced.
AHVI
DLVI
ALVI
6-5.
Vddd
Vdda
Vdda
1.71V-5.5V 1.70V-5.45V in
1.71V-5.5V 1.70V-5.45V in
1.71V-5.5V 5.75V
Voltage
Normal
Range
250 mV
increments
250 mV
increments
Available Trip
Settings
PRELIMINARY
Accuracy
±2%
±2%
±2%
6.3.1.2 Other Reset Sources
6.4 I/O System and Routing
PSoC I/Os are extremely flexible. Every GPIO has analog and
digital I/O capability. All I/Os have a large number of drive modes,
which are set at POR. PSoC also provides up to four individual
I/O voltage domains through the Vddio pins.
There are two types of I/O pins on every device; those with USB
provide a third type. Both General Purpose I/O (GPIO) and
Special I/O (SIO) provide similar digital functionality. The primary
differences are their analog capability and drive strength.
Devices that include USB also provide two USBIO pins that
support specific USB functionality as well as limited GPIO
capability.
All I/O pins are available for use as digital inputs and outputs for
both the CPU and digital peripherals. In addition, all I/O pins can
generate an interrupt. The flexible and advanced capabilities of
the PSoC I/O, combined with any signal to any pin routability,
greatly simplify circuit design and board layout. All GPIO pins can
be used for analog input, CapSense
while SIO pins are used for voltages in excess of Vdda and for
programmable output voltages.
XRES - External Reset
CY8C52 has either a single GPIO pin that is configured as an
external reset or a dedicated XRES pin. Either the dedicated
XRES pin or the GPIO pin, if configured, holds the part in reset
while held active (low). The response to an XRES is the same
as to an IPOR reset.
The external reset is active low. It includes an internal pull up
resistor. XRES is active during sleep and hibernate modes.
SRES - Software Reset
A reset can be commanded under program control by setting
a bit in the software reset register. This is done either directly
by the program or indirectly by DMA access. The response to
a SRES is the same as after an IPOR reset.
Another register bit exists to disable this function.
WRES - Watchdog Timer Reset
The watchdog reset detects when the software program is no
longer being executed correctly. To indicate to the watchdog
timer that it is running correctly, the program must periodically
reset the timer. If the timer is not reset before a user-specified
amount of time, then a reset is generated.
Note IPOR disables the watchdog function. The program must
enable the watchdog function at an appropriate point in the
code by setting a register bit. When this bit is set, it cannot be
cleared again except by an IPOR power on reset event.
Features supported by both GPIO and SIO:
User programmable port reset state
Separate I/O supplies and voltages for up to four groups of I/O
Digital peripherals use DSI to connect the pins
Input or output or both for CPU and DMA
Eight drive modes
Every pin can be an interrupt source configured as rising
edge, falling edge or both edges. If required, level sensitive
interrupts are supported through the DSI
Dedicated port interrupt vector for each port
PSoC
®
5: CY8C52 Family Data Sheet
[4]
, and LCD segment drive,
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