xe8802 Semtech Corporation, xe8802 Datasheet - Page 95

• Manufacturer Part Number: xe8802
• Description: Data Acquisition Soc With 16+10 Bit Zoomingadc? Embedded Risc Controller And Lcd Driver
• Manufacturer: Semtech Corporation

write to RegUartTx
write to RegUartTx
14.8.3
On detection of the start bit, the UartRxBusy bit is set. On detection of the stop bit, the received data are
transferred from the internal shift register to the register RegUartRx. At the same time, the UartRxFull bit is set
and an interrupt is generated on Irq_uart_Rx. This indicates that new data is available in RegUartRx. The timing
diagram is shown in Figure 14-2.
The UartRxFull bit is cleared when RegUartRx is read. If the register was not read before the receiver transfers a
new word to it, the bit UartRxOErr (overflow error) is set and the previous contents of the register are lost.
UartRxOErr is cleared by writing any data to RegUartRxSta.
The bit UartRxSErr is set if a start error has been detected. The bit is updated at data transfer to RegUartRx.
The bit UartRxPErr is set if a parity error has been detected, i.e. the received parity bit is not equal to the
calculated parity of the received data. The bit is updated at data transfer to RegUartRx.
The bit UartRxFErr in RegUartRxSta shows that a frame error has been detected. No stop bit has been detected.
© Semtech 2006
Asynchronous Transmission
Asynchronous Transmission (back to back)
reguarttx_shift
reguarttx_shift
UartTxBusy
UartTxBusy
RegUartTx
Irq_uart_Tx
RegUartTx
Irq_uart_Tx
UartTxFull
UartTxFull
shift clock
shift clock
Figure 14-1. Uart transmission timing diagram.
Reception
Tx
Tx
word 1
word 1
word 1
start
word 2
word 1
start
word 2
word 1
b0
XE8802 Sensing Machine Data Acquisition MCU
b0
b1
14-6
b6/7
with ZoomingADC™ and LCD driver
stop
b6/7
word 2
start
parity
stop
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