ade7753 Analog Devices, Inc., ade7753 Datasheet - Page 25

• Manufacturer Part Number: ade7753
• Description: Active And Apparent Energy Metering Ic With Di/dt Sensor Interface
• Manufacturer: Analog Devices, Inc.

The upper 52-bit of the internal register are divided by
VADIV. If the value in the VADIV register is equal to 0 then
the internal active Energy register is divided by 1. VADIV is
an 8-bit unsigned register. The upper 24-bit are then written
in the 24-bit Apparent Energy register (VAENERGY[23:0]).
RVAENERGY register (24 bits long) is provided to read the
Apparent Energy. This register is reset to zero after a read
operation.
Figure 45 shows this Apparent Energy accumulation for full
scale signals (sinusoidal) on the analog inputs. The three
curves displayed, illustrate the minimum time it takes the
energy register to roll-over when the VA Gain registers
content is equal to 7FFh, 000h and 800h. The VA Gain
register is used to carry out an apparent power calibration in
the ADE7753. As shown, the fastest integration time will
occur when the VA Gain register is set to maximum full scale,
i.e., 7FFh.
Note that the Apparent Energy register contents roll-over to
full-scale negative (80,0000h) and continue increasing in
value when the power or energy flow is positive - see Figure
46.
By using the Interrupt Enable register, the ADE7754 can be
configured to issue an interrupt (IRQ) when the Apparent
Energy register is half full (positive or negative) or when an
over/under flow occurs.
REV. PrF 10/02
Figure 46- Energy register roll-over time for full-scale
VAENERGY[23:0]
APPARENT POWER
FF,FFFFh
80,0000h
20,0000h
40,0000h
00,0000h
Figure 45- ADE7753 Apparent Energy calculation
AD055h
00000h
power (Minimum & Maximum Power Gain)
T
T
4.9
time (nT)
Apparent Power
Signal - P
+
7.4
+
VADIV
11.1
PRELIMINARY TECHNICAL DATA
47
46
23
VAENERGY[23:0]
ACCUMULATED (INTEGRATED) IN
THE APPARENT ENERGY REGISTER
APPARENT POWER ARE
14.8
0
VAGAIN = 7FFh
VAGAIN = 000h
VAGAIN = 800h
0
0
Time
(minutes)
–25–
Integration times under steady load
As mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 1.1µs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
VAGAIN register set to 000h, the average word value from
Apparent Power stage is AD055h - see Apparent Power output
range. The maximum value which can be stored in the
Apparent Energy register before it over-flows is 2
FF,FFFFh. As the average word value is added to the
internal register which can store 2
before it overflows, the integration time under these condi-
tions with VADIV=0 is calculated as follows:
Time
When VADIV is set to a value different from 0, the integra-
tion time varies as shown on Equation 23.
Time = Time
LINE APPARENT ENERGY ACCUMULATION
The ADE7753 is designed with a special Apparent Energy
accumulation mode which simplifies the calibration process.
By using the on-chip zero-crossing detection, the ADE7753
accumulates the Apparent Power signal in the LVAENERGY
register for an integral number of half cycles, as shown in
Figure 47. The line Apparent energy accumulation mode is
always active.
The number of half line cycles is specified in the LINCYC
register. LINCYC is an unsigned 16-bit register. The
ADE7753 can accumulate Apparent Power for up to 65535
combined half cycles. Because the Apparent Power is inte-
grated on the same integral number of line cycles as the Line
Active Energy register, these two values can be compared
easily. The active and apparent Energy are calculated more
accurately because of this precise timing control and provide
all the information needed for Reactive Power and Power
Factor calculation. At the end of an energy calibration cycle
the CYCEND flag in the Interrupt Status register is set. If the
CYCEND mask bit in the Interrupt Mask register is enabled,
the IRQ output will also go active low. Thus the IRQ line can
also be used to signal the end of a calibration.
The Line Apparent Energy accumulation uses the same
signal path as the Apparent Energy accumulation. The LSB
size of these two registers is equivalent.
CHANNEL 2
FROM
ADC
Figure 47 - ADE7753 Apparent Energy Calibration
=
LPF1
7FFF,
Apparent Power
WDIV=0
AD055h
DETECTION
CROSSING
FFFF,
ZERO
x VADIV
VADIV[7:0]
FFFFh
LINECYC[15:0]
CALIBRATION
CONTROL
+
×
+
1.2
48
µ
- 1 or 7FFF,FFFF,FFFFh
LVAENERGY[23:0]
46
23
s
=
8
88
ADE7753
(23)
s
0
=
1
LVAENERGY REGISTER IS
UPDATED EVERY LINECYC
ZERO-CROSSINGS WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
0
4
8 .
min
24
or