ade7753 Analog Devices, Inc., ade7753 Datasheet - Page 9

• Manufacturer Part Number: ade7753
• Description: Active And Apparent Energy Metering Ic With Di/dt Sensor Interface
• Manufacturer: Analog Devices, Inc.

ANALOG INPUTS
The ADE7753 has two fully differential voltage input chan-
nels. The maximum differential input voltage for input pairs
V1P/V1N and V2P/V2N are ±0.5V. In addition, the maxi-
mum signal level on analog inputs for V1P/V1N and V2P/
V2N are ±0.5V with respect to AGND.
Each analog input channel has a PGA (Programmable Gain
Amplifier) with possible gain selections of 1, 2, 4, 8 and 16.
The gain selections are made by writing to the Gain regis-
ter—see Figure 2. Bits 0 to 2 select the gain for the PGA in
Channel 1 and the gain selection for the PGA in Channel 2
is made via bits 5 to 7. Figure 1 shows how a gain selection
for Channel 1 is made using the Gain register.
In addition to the PGA, Channel 1 also has a full scale input
range selection for the ADC. The ADC analog input range
selection is also made using the Gain register—see Figure 2.
As mentioned previously the maximum differential input
voltage is 1V. However, by using bits 3 and 4 in the Gain
register, the maximum ADC input voltage can be set to 0.5V,
0.25V or 0.125V. This is achieved by adjusting the ADC
reference—see ADE7753 Reference Circuit. Table I below sum-
marizes the maximum differential input signal level on
Channel 1 for the various ADC range and gain selections.
Max Signal
Channel 1
0.5V
0.25V
0.125V
0.0625V
0.0313V
0.0156V
0.00781V
REV. PrF 10/02
CH1OS[7:0]
Bit 0 to 5: Sign magnitude coded offset correction
Bit 6: Not used
Bit 7: Digital Integrator (On=1, Off=0; default ON)
Maximum input signal levels for Channel 1
V in
V1P
V1N
Figure 1— PGA in Channel 1
ADC Input Range Selection
0.5V
Gain = 1 —
Gain = 2 Gain = 1 —
Gain = 4 Gain = 2 Gain = 1
Gain = 8 Gain = 4 Gain = 2
Gain = 16 Gain = 8 Gain = 4
—
—
GAIN[7:0]
+
-
Table I
k.V in
0.25V
Gain = 16 Gain = 8
—
PRELIMINARY TECHNICAL DATA
Gain (k)
selection
+
Offset
Adjust
(±50mV)
0.125V
—
Gain = 16
–9–
PGA 2 Gain Select
000 = x1
001 = x2
010 = x4
011 = x8
100 = x16
It is also possible to adjust offset errors on Channel 1 and
Channel 2 by writing to the Offset Correction Registers
(CH1OS and CH2OS respectively). These registers allow
channel offsets in the range ±20mV to ±50mV (depending on
the gain setting) to be removed. Note that it is not necessary
to perform an offset correction in an Energy measurement
application if HPF in Channel 1 is switched on. Figure 3
shows the effect of offsets on the real power calculation. As
can be seen from Figure 3, an offset on Channel 1 and
Channel 2 will contribute a dc component after multiplica-
tion. Since this dc component is extracted by LPF2 to
generate the Active (Real) Power information, the offsets will
have contributed an error to the Active Power calculation.
This problem is easily avoided by enabling HPF in Channel
1. By removing the offset from at least one channel, no error
component is generated at dc by the multiplication. Error
terms at Cos(w.t) are removed by LPF2 and by integration of
the Active Power signal in the Active Energy register (AEN-
ERGY[23:0]) – see Energy Calculation.
The contents of the Offset Correction registers are 6-Bit, sign
and magnitude coded. The weighting of the LSB size
depends on the gain setting, i.e., 1, 2, 4, 8 or 16. Table II
below shows the correctable offset span for each of the gain
settings and the LSB weight (mV) for the Offset Correction
registers. The maximum value which can be written to the
offset correction registers is ±31 decimal —see Figure 4.
Figure 4 shows the relationship between the Offset Correc-
tion register contents and the offset (mV) on the analog inputs
for a gain setting of one. In order to perform an offset
adjustment, The analog inputs should be first connected to
AGND, and there should be no signal on either Channel 1
or Channel 2. A read from Channel 1 or Channel 2 using the
Figure 3— Effect of channel offsets on the real power cal-
V OS .I OS
Figure 2— ADE7753 Analog Gain register
V.I
2
0
Channel 1 and Channel 2 PGA Control
*Register contents show power on defaults
0
7
0
6
GAIN REGISTER*
0
5
DC component (including error term) is
extracted by the LPF for real power
calculation
V OS .I
0
I OS .V
frequency (rad/s)
4
culation
0
3
2
0
2
0
1
0
0
ADDR: 0FH
ADE7753
PGA 1 Gain Select
000 = x1
001 = x2
010 = x4
011 = x8
100 = x16
Channel 1 Full Scale Select
00 = 0.5V
01 = 0.25V
10 = 0.125V