atam894 ATMEL Corporation, atam894 Datasheet
atam894
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atam894 Summary of contents
Page 1
... Watchdog, POR and Brown-out Function 1. Description The ATAM894 is a member of the Atmel’s family of 4-bit single chip microcontrollers with 8K 8-bit EEPROM program memory based on the 4-K MTP version ATAM893 and fully compatible with this MTP and the ROM versions ATAR090/890 and ATAR092/892 ...
Page 2
... Bi-directional I/O line of Port 1.3 – 14 BP63 I/O Bi-directional I/O line of Port 6.3 T3I Timer 3 input 15 BP20 I/O Bi-directional I/O line of Port 2.0 16 BP21 I/O Bi-directional I/O line of Port 2.1 – 17 BP22 I/O Bi-directional I/O line of Port 2.2 – 18 BP23 I/O Bi-directional I/O line of Port 2.3 – ATAM894 VDD 22 VSS 3 BP43/INT3/SD BP40/INT3/ BP42/T2O BP53/INT1 5 ...
Page 3
... Data Memory The ATAM894 contains an internal data EEPROM that is organized as two pages necessary to be compatible with the ROM parts, only one page must be used with the flash part. Also for compatibility reasons the access to the EEPROM is handled via the MCL (serial interface the corresponding ROM parts ...
Page 4
... The MARC4 is designed for the high-level programming language qFORTH. The core includes both, an expression and a return stack. This architecture enables high-level language programming without any loss of efficiency or code density. Figure 5-1. ATAM894 4 MARC4 Core Reset Program ...
Page 5
... Kbytes. The upper 2 Kbytes may be exchanged by ROM banking, thus allowing to address a maximum of 10 Kbytes user program. 8 Kbytes of program memory are available within the ATAM894. The lowest user (EEP)ROM address segment is taken 512-byte zero page which contains predefined start addresses for interrupt service routines and special subroutines accessible with single byte instructions (SCALL) ...
Page 6
... For linear code (no calls or branches) the program counter is incremented with every instruction cycle branch-, call-, return-instruction or an interrupt is executed, the program counter is loaded with a new address. The program counter is also used with the table instruction to fetch 8-bit wide ROM constants. ATAM894 6 RAM Map RAM ...
Page 7
... ROM Banking Register (RBR) The ROM banking register is a 4-bit register whereby the ATAM894 only uses 2 bit. This register indicates which ROM bank is presently being addressed. The RBR is accessed with a standard qFORTH peripheral read or write instruction (IN or OUT, port address 'D' hex). ...
Page 8
... The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two ele- ments of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU operations affect the carry/borrow and branch flag in the condition code register (CCR). ATAM894 8 4679D–4BMCU–05/05 ...
Page 9
... ALU Zero-address Operations RAM SP TOS-1 TOS-2 TOS-3 TOS-4 CCR ”Peripheral Modules” on page ”Emulation” on page Table 5-1 on page 11). The programmer can postpone the processing ATAM894 TOS ALU 22. The I/O bus is internal and is 92). ”Peripheral Modules” on page 22). 9 ...
Page 10
... In MARC4 this is extremely short (taking between machine cycles depending on the state of the core). Figure 5-6. Interrupt Handling INT3 4 3 INT3 active Main/ Autosleep ATAM894 10 INT7 INT7 active RTI INT5 INT5 active RTI INT2 INT2 pending Time RTI INT2 active RTI SWI0 INT0 pending ...
Page 11
... Hardware Interrupts In the ATAM894, there are eleven hardware interrupt sources with seven different levels. Each source can be masked individually by mask bits in the corresponding control registers. An over- view of the possible hardware configurations is shown in 4679D–4BMCU–05/05 ...
Page 12
... Figure 5-7. 5.3.1 Power-on Reset and Brown-out Detection The ATAM894 has a fully integrated power-on reset and brown-out detection circuitry. For reset generation no external components are needed. These circuits ensure that the core is held in the reset state until the minimum operating supply voltage has been reached. A reset condition will also be generated should the supply voltage drop momentarily below the minimum operating level except when a power down mode is acti- vated (the core is in SLEEP mode and the peripheral clock is stopped) ...
Page 13
... BOT = 1.5 ms (typically) d BOT = 1, low brown-out voltage threshold 1.7V (is reset value). BOT = 0, high brown-out voltage threshold 2.0V. = 1.3V. The VMS bit indicates if the supervised voltage is below BG rise across the default BOT voltage level (1.7V falls below the brown-out voltage threshold. Two DD ATAM894 ...
Page 14
... VMC: Write VMST: Read VM2: V oltage monitor M ode bit 2 VM1: V oltage monitor M ode bit 1 VM0: V oltage monitor M ode bit 0 Table 5-3. VM2 ATAM894 14 Voltage Monitor Voltage monitor BP41/ IN VMI VMC: VM2 VM1 VM0 VMST: - Bit 3 Bit 2 VM2 VM1 – ...
Page 15
... Clock Module The ATAM894 contains a clock module with 4 different internal oscillator types: two RC-oscilla- tors, one 4-MHz crystal oscillator and one 32-kHz crystal oscillator. The pins OSC1 and OSC2 are the interface to connect a crystal either to the 4-MHz the 32-kHz crystal oscillator. ...
Page 16
... The SYSCL can supply the core and the peripherals and the SUBCL can supply only the peripherals with clocks. The modes for clock sources are programmable with the OS1 bit and OS0 bit in the SC register and the CCS bit in the CM register. ATAM894 16 RC- ...
Page 17
... Oscillator Circuits and External Clock Input Stage The ATAM894 series consists of four different internal oscillators: two RC-oscillators, one 4-MHz crystal oscillator, one 32-kHz crystal oscillator and one external clock input stage. 5.5.2.1 RC-oscillator 1 Fully Integrated For timing insensitive applications possible to use the fully integrated RC-oscillator 1. It operates without any external components and saves additional costs. The RC-oscillator 1 cen- ter frequency tolerance is better than ± ...
Page 18
... For example: An output frequency at the RC-oscillator MHz can be obtained by connect- ing a resistor R Figure 5-15. RC-oscillator 2 5.5.2.4 4-MHz Oscillator The ATAM894 4-MHz oscillator options need a crystal or ceramic resonator connected to the OSC1 and OSC2 pins to establish oscillation. All the necessary oscillator circuitry, with the exception of the actual crystal, resonator, C Figure 5-16. 4-MHz Crystal Oscillator Note: ...
Page 19
... This results in an additional delay of about 4 ms for the 4-MHz crystal and about 500 ms for the 32-kHz crystal. Oscin 4Out 4Out * 4-MHz oscillator C Osc-Stop 1 Stop Oscout * C 2 Oscin 32Out 32Out 32-kHz oscillator 1 Oscout 2 ATAM894 19 ...
Page 20
... CCS CSS1 CSS0 Table 5-6. 5.5.3.2 System Configuration Register (SC) SC: write BOT OS1 OS0 ATAM894 20 Bit 3 Bit 2 Bit 1 NSTOP CCS CSS1 Not STOP peripheral clock NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode ...
Page 21
... V total The ATAM894 has various power-down modes. During the sleep mode the clock for the MARC4 core is stopped. With the NSTOP bit in the clock management register (CM programmable if the clock for the on-chip peripherals is active or stopped during the sleep mode. If the clock for the core and the peripherals is stopped the selected oscillator is switched off ...
Page 22
... Addr. (ASW) = Auxililiary Switch Module Address Addr. (Mx) = Module Mx Address Addr. (SPort) = Subport Address Prim._Data = Data to be written into Primary Register Aux._Data = Data to be written into Auxiliary Register Aux._Data (lo) = Data to be written into Auxiliary Register (low nibble) ATAM894 22 Example of I/O Addressing Module M1 (Address Pointer) Bank of Subaddress Reg ...
Page 23
... Reserved – Reserved W 0000b Timer 3 control register R x000b Timer 3 status register – Reserved W 1111b Voltage monitor control register R xx11b Voltage monitor status register ATAM894 Module See Type Page M3 page 24 M2 page 26 page 26 M3 page 20 M3 page 13 M2 page 20 M2 page 29 ...
Page 24
... OUT instruction. After RESET all output latches are set to '1' and the port is switched to input mode instruction reads the condition of the associ- ated pins. Note: ATAM894 24 2-bit wide bi-directional ports with automatic full bus width direction switching 4-bit wide bit-wise-programmable I/O port ...
Page 25
... I/O Bus (Data out P1DATy R Reset (Direction) OUT Master reset (1) Switched (1) pull-up ( (1) (1) Switched Flash options pull-down by an additional internal strong pull-up transistor. This during reset by any external circuitry rep- SS ATAM894 Static pull-up BP1y Static pull-down 25 ...
Page 26
... Note: 6.2.2.2 Port 2 Control Register (P2CR) P2CR Note: Table 6-2. Code ATAM894 26 Bi-directional Port 2 I/O Bus (Data out) I/O Bus D Q P2DATy S Master reset I/O Bus P2CRy ...
Page 27
... P52M1 P51M2 Figure 6-4 on page 27 22). Switched pull-up (1) ( (1) ( (1) (1) Switched Flash options pull-down Data in Bidir. Port IN_Enable I/O-bus Data in Bidir. Port IN_Enable Decoder P51M1 P50M2 P50M1 ATAM894 and Fig Static pull-up BP5y Static pull-down BP5 BP5 1376 27 ...
Page 28
... VM or SSI). The I/O pins for the SC and SD lines have an additional mode to generate an SSI-interrupt. All four Port 4 pins can be individually switched by the P4CR register. shows the internal interfaces to bi-directional Port 4. ATAM894 28 Bit 3 Bit 2 ...
Page 29
... Flash options pull-down Primary register address: '4'hex Bit 0 P4DAT0 Reset value: 1111b Auxiliary register address: '4'hex Bit 2 Bit 1 Bit 0 P41M1 P40M2 P40M1 Reset value: 1111b Bit 6 Bit 5 Bit 4 P43M1 P42M2 P42M1 Reset value: 1111b ATAM894 V DD Static (1) pull-up BPxy Static (1) pull-down 29 ...
Page 30
... Port 6 Data Register (P6DAT) P6DAT 6.2.5.2 Port 6 Control Register (P6CR) P6CR P6xM2, P6xM1 Table 6-5. Code ATAM894 30 Second Write Cycle Code – ...
Page 31
... T2I MUX DCG TOG2 Receive buffer MUX 8-bit shift register Transmit buffer Timer 1 Watchdog Interval/Prescaler Timer 3 Control Demodu- lator 3 Modu- lator 3 Timer 2 Modu- lator 2 I/O bus Control 8-bit Counter 2/2 Compare 2/2 SSI SCL Control ATAM894 NRST INT2 T3O INT5 T2O INT4 SC SD INT3 31 ...
Page 32
... The watchdog timer operation mode and the time interval for the watchdog reset can be pro- grammed via the watchdog control register (WDC). Figure 6-8. ATAM894 32 yes) the output T1OUT is stopped (T1OUT = 0). Nevertheless, the Timer 1 can be Timer 1 Module ...
Page 33
... Timer 1 Control bit 0 T1C2 T1BP T1IM T1MUX MUX for interval timer Q8 Q11 Q14 SUBCL Q6 Q8 Q11 Q14 Watchdog Divider/8 WDCL Address: '7'hex — Subaddress: '8'hex Bit 0 T1C0 Reset value: 1111b ATAM894 T1IM=0 INT2 T1IM=1 T1OUT RESET Divider (NRST) RESET Read of the CWD register 33 ...
Page 34
... Timer 1 Control Register 2 (T1C2) T1C2 Note: T1BP T1CS T1IM 6.3.1.3 Watchdog Control Register (WDC) WDC Note: WDL WDR WDT1 WDT0 ATAM894 34 Timer 1 Control Bits Time Interval with T1C1 T1C0 Divider SUBCL SUBCL SUBCL SUBCL ...
Page 35
... WDT0 Divider t = 1/32 kHz in 0 512 15.625 ms 1 2048 62 16384 1 131072 sleep and OSC-Stop no). All other clock sources supply no clock signal in SLEEP if ATAM894 Delay Time to Reset with t = 1/(2/1 MHz) in 0.256 ms/0.512 ms 1.024 ms/2.048 ms 0.5 s 8.2 ms/16 65.5 ms/131 ms yes) as well as in POWER-DOWN (CPU core 35 ...
Page 36
... For 8-bit compare data value: For 4-bit compare data value: Figure 6-10. Timer 2 T2I SYSCL CL2/1 T1OUT 4-bit Counter 2/1 TOG3 SCL RES T2C Compare 2/1 T2CO1 ATAM894 P4CR T2M1 CL2/2 DCG 8-bit Counter 2/2 OVF1 POUT RES Control Compare 2/2 ...
Page 37
... RES CM2 8-bit compare 8-bit register T2RM POUT OVF2 DCG 8-bit counter RES CM2 8-bit compare 8-bit register T2RM Timer 2 output mode and T2OTM-bit T2OTM T2IM T2CTM Timer 2 output mode and T2OTM-bit T2OTM T2IM T2CTM ATAM894 TOG2 INT4 DCGO TOG2 INT4 37 ...
Page 38
... Figure 6-13. 4-/8-bit Compare Counter T2I CL2/2 DCG SYSCL P4CR P41M2, 1 T2D1, 0 TOG3 T1OUT CL2/1 MUX SYSCL SCL T2CS1, 0 ATAM894 38 OVF2 8-bit counter RES CM2 8-bit compare Timer 2 output mode and T2OTM-bit 8-bit register T2RM T2OTM 4-bit counter RES CM1 4-bit compare ...
Page 39
... Figure 6-15. Interrupt Timer/Square Wave Generator — the Output Toggles with Each Edge 4679D–4BMCU–05/05 DCGO SO TOG2 RE Bi-phase/ Manchester modulator FE SSI OMSK T2M2 Compare Match Event Input Counter 2 T2R Counter 2 CMx INT4 T2O M2 Toggle S2 S1 RES/SET M2 T2TOP T2OS2 ATAM894 T2O S3 Modulator 3 T2O ...
Page 40
... Figure 6-16. Pulse Generator — the Timer Output Toggles with the Timer Start if the T2TS bit Counter 2 Counter 2 Toggle Mode Timer 2 compare match toggles the output flip-flop (M2) Figure 6-17. Pulse Generator — the Timer Toggles with Timer Overflow and Compare Match Counter 2 Counter 2 ATAM894 40 is Set Input T2R 0 0 ...
Page 41
... Counter 2 Counter = compare register (= 2) TOG2 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 SO T2O TOG2 Bit T2O Data: 00110101 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 8-bit SR data Bit ATAM894 Bit 12 Bit ...
Page 42
... The resolution at the pulse-width modulation Timer 2 mode 1 is 12-bit and all other Timer 2 modes are 8-bit. Figure 6-22. PWM Modulation Input clock Counter 2/2 Counter 2/2 ATAM894 42 TOG2 ...
Page 43
... Timer 2 Duty cycle bit 1 Timer 2 Duty cycle bit 0 Timer 2 Mode Select bit 1 Timer 2 Mode Select bit 0 22. The alternate functions of the Ports Address: '7'hex — Subaddress: '0'hex Bit 0 T2R Reset value: 0000b Address: '7'hex — Subaddress: '1'hex Bit 0 T2MS0 Reset value: 1111b ATAM894 43 ...
Page 44
... The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at the duty cycle generator output depends on the duty cycle and the Timer 2 prescaler setting. The DCG-stage can also be used as an additional programmable prescaler for Timer 2. Figure 6-23. DCG Output Signals ATAM894 44 Timer 2 Duty Cycle Bits T2D0 ...
Page 45
... ATAM894 Address: '7'hex — Subaddress: '2'hex Reset value: 1111b Clock Output Toggle mode: a Timer 2 compare match toggles the output flip-flop (M2) T2O Duty cycle burst generator 1: the DCG output signal (DCG0) is given to the output and gated by the output flip-flop (M2) ...
Page 46
... Table 6-12. Timer 2 Output Mode 6.3.2.12 Timer 2 COmpare Register 1 (T2CO1) T2CO1 In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0. 6.3.2.13 Timer 2 COmpare Register 2 (T2CO2) Byte Write T2CO2 ATAM894 46 Bit 3 Bit 2 Bit 1 T2OTM T2CTM T2RM Timer 2 Overflow Toggle Mask bit T2OTM = 0, disable overflow toggle T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles output flip-flop (TOG2) ...
Page 47
... I/O-bus CP3 T3CP T3C Compare 3/2 Control T3CO2 T3CM1 I/O-bus yes), this timer input is stopped too. The counter is readable via its T3M T3EX T3I Demodu- lator 3 CM31 RES INT5 T3ST TOG3 SO Modulator 3 Control M2 TOG2 T3CM2 Timer 2 SSI ATAM894 SCI SI T3O SSI 47 ...
Page 48
... The compare mode registers T3M1 and T3M2 contain the mask bits for enabling or disabling these actions. The counter can also be enabled to execute single actions with one or both compare registers. If this mode is set the corresponding compare match event is generated only once after the counter starts. ATAM894 48 T3I Control D ...
Page 49
... T3O. The counter value can be read by the software via the capture register. Figure 6-26. Counter Reset with Each Compare Match 4679D–4BMCU–05/05 T3R Counter 3 CM31 CM32 INT5 T3O 0 x 255 ATAM894 ...
Page 50
... The edge can be selected by the pro- grammable edge decoder of the timer input stage. If single-action mode is activated for one or both compare registers the trigger signal restarts the single action. Figure 6-29. Externally Triggered Counter Reset and Start Combined with Single-action Mode Counter 3 ATAM894 50 CL3 T3R 0 ...
Page 51
... Capture value = 0 Register Timer/Counter, External Trigger Restart and External Capture (with T3I Input) Carrier Frequency Burst Modulation Controlled by Timer 2 Output Toggle Flip-Flop (M2) Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO Capture value = 11 ATAM894 Capture value = 4 51 ...
Page 52
... Timer 2. The counter is driven by an internal or external clock source (see section “Combination Mode 7”). Figure 6-32. Pulse-width Modulation Counter 3 ATAM894 52 T3R ...
Page 53
... CM31 = SCI Reset Counter 3 0 SR-DATA Bit 7 Manchester demodulation mode BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 Bi-phase demodulation mode Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 ATAM894 BIT Bit 1 Bit 0 53 ...
Page 54
... The modulator can be started with the start of the shift register (SIR = 0) and stopped either by a shift register stop (SIR = 1) or compare match event of stage 1 of Timer 2. For this task, the Timer 2 must be used in mode 3 and the prescaler stage must be supplied by the internal shift clock of the shift register. Figure 6-36. Modulator 3 ATAM894 54 T3R T3I 0 ...
Page 55
... ATAM894 T3M SCI Demodulator 3 SI Res Counter 3 CM31 Reset Counter 3 Control Address: 'B'hex — Subaddress: '0'hex Reset value: 1111b Timer 3 Modes Timer/counter with a read access Timer/counter, external capture and external trigger restart mode (T3I) ...
Page 56
... Note: 6.3.3.8 Timer 3 Control Register 1 (T3C) Write Write T3EIM T3TOP T3TS T3R 6.3.3.9 Timer 3 Status Register 1 (T3ST) Read Read T3ED T3C2 T3C1 Note: ATAM894 56 Timer 3 Mode Select Bits (Continued) T3M3 T3M2 T3M1 T3M0 ...
Page 57
... T3CS1 TCS0 Counter 3 Input Signal (CL3 System clock (SYSCL Output signal of Timer 2 (POUT Output signal of Timer 1 (T1OUT External input signal from T3I edge detect Address: 'B'hex — Subaddress: '1'hex Bit 1 Bit 0 T3CS1 T3CS0 Reset value: 1111b ATAM894 57 ...
Page 58
... T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1 6.3.3.13 Timer 3 Compare Mode Register 2 (T3CM2) T3CM2 T3SM2 T3TM2 T3RM2 T3IM2 T3CM2 contains the mask bits for the match event of Counter 3 compare register 2 ATAM894 58 Bit 3 Bit 2 Bit 1 T3SM1 T3TM1 T3RM1 Timer 3 Single action Mask bit 1 T3SM1 = 0, disables single-action compare mode T3SM1 = 1, enables single-compare mode ...
Page 59
... Bit 3 Bit 2 Bit 1 Bit 0 Address: 'B'hex — Subaddress: ’4'hex High Nibble Bit 7 Bit 6 Bit 5 Bit 4 Low Nibble Bit 3 Bit 2 Bit 1 Bit 0 ATAM894 Reset value: 1111b Reset value: 1111b Reset value: 1111b Reset value: 1111b Reset value: xxxxb Reset value: xxxxb 59 ...
Page 60
... MCL_SC) which act as a two-wire chip- to-chip link. The MCL can be activated by the MCL control bit. Should these MCL pads be used by the SSI, the standard SD and SC pins are not required and the correspond- ing Port 4 ports are available as conventional data ports. ATAM894 60 4679D–4BMCU–05/05 ...
Page 61
... Thus, data can be simultaneously received and transmitted if required. 4679D–4BMCU–05/05 I/O-bus SIC1 SIC2 SC SSI-Control SO /2 8-bit Shift Register MSB Shift_CL STB Transmit Buffer ”MCL Bus Protocol” on page ATAM894 Timer 2/Timer 3 SISC SO SI SCI Control INT3 Output SI LSB SRB Receive Buffer I/O-bus 65). SC ...
Page 62
... SSI will continue clocking in the next telegram. Should, however, the first telegram not have been read (SRDY = 1), then the SSI will stop, temporarily holding the second telegram in the shift register until a certain point of time when the controller is able to service the receive buffer. In this way no data is lost or overwritten. ATAM894 62 SC (rising edge) ...
Page 63
... Write STB Write STB (tx data 2) (tx data 3) lsb msb data 3 Read SRB Read SRB (rx data 1) (rx data 2) ATAM894 lsb 0 lsb Read SRB (rx data 3) 63 ...
Page 64
... SIR bit. So, if the SIR bit is set to '1' in telegram, the SSI will complete the current transfer and terminate the dialog with an MCL stop condition. Figure 6-42. Example of MCL Transmit Dialog Interrupt (IFN = 0) Interrupt (IFN = 1) ATAM894 64 Start SC msb lsb ...
Page 65
... Start SC msb lsb data 1 SRDY ACT Interrupt (IFN = 0) Interrupt (IFN = 1) SIR SDD Write STB (tx data 1) ATAM894 Stop msb lsb data 2 Read SRB (rx data 2) 65 ...
Page 66
... To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and the Inter- rupt Function (IFN) while the Port 4 interrupts are enabled by setting appropriate control bits in P4CR register. ATAM894 66 (1) (2) ...
Page 67
... Figure 6-47. SSI Output Masking Function CL2/1 SCL SC TOG2 POUT /2 T1OUT SYSCL 4679D–4BMCU–05/05 U505M SCL MCL_SC V DD BP40/SC Microcontroller BP10 Timer 2 4-bit counter 2/1 Compare 2/1 CM1 SSI-control SO 8-bit shift register MSB Shift_CL ATAM894 SDA Multi-chip link MCL_SD V SS BP43/SD BP13 OMSK SO Control Output SI LSB 67 ...
Page 68
... In transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY = 1). • Setting SIR bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only). • In MCL modes, writing SIR generates a start condition and writing a 1 generates a stop condition. ATAM894 68 Bit 3 Bit 2 SIR SCD ...
Page 69
... SDD controls port directional control and defines the reset function for the SRDY-flag Auxiliary register address: 'A'hex Bit 1 Bit 0 SM0 SDD SSI Mode 8-bit NRZ-data changes with the rising edge of SC 8-bit NRZ-data changes with the falling edge of SC 9-bit two-wire MCL mode 8-bit two-wire pseudo MCL mode (no acknowledge) ATAM894 Reset value: 1111b 69 ...
Page 70
... Serial Transmit Buffer (STB) – Byte Write First write cycle Second write cycle The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift reg- ister and starts shifting with the most significant bit. ATAM894 70 Bit 3 Bit 2 Bit 1 ...
Page 71
... Bit 4 Reset value: xxxxb Bit 1 Bit 0 Reset value: xxxxb I/O-bus T2M2 T2O 8-bit Counter 2/2 OUTPUT OVF2 TOG2 Compare 2/2 MOUT INT4 Bi-phase Manchester Timer 2 modulator T2CO2 modulator output-stage SO Control SISC Control SO INT3 SC MCL_SC Output MCL_SD SI SD LSB SRB Receive buffer I/O-bus ATAM894 71 ...
Page 72
... Timer 2 output mode 4: Figure 6-50. Bi-phase Modulation 1 Combination Mode 3: Manchester Modulation 1 SSI mode 1: Timer 2 mode Timer 2 output mode 5: ATAM894 72 8-bit NRZ and internal data SO output to the Timer 2 modulator stage 8-bit compare counter with 4-bit programmable prescaler and DCG Duty cycle burst generator ...
Page 73
... Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit MSM Timer 2 Mode 3 SCL Counter 2/1 = Compare Register 2 Counter 2/1 OMSK T2O 8-bit SR data ATAM894 1 Bit 0 Bit ...
Page 74
... The SSI has a special mode to supply the prescaler via the shift clock. The control output signal (OMSK) of the SSI is used as a stop signal for the modulator. This is an example for a 13-bit Bi- phase telegram. Figure 6-53. Bi-phase Modulation Counter 2/1 ATAM894 74 8-bit shift register internal data output (SO) to the Timer 2 modulator stage 8-bit compare counter and 4-bit prescaler ...
Page 75
... Timer 3 FSK modulation with shift register data (SO) T3M T3EX T3I Demodu- lator 3 CM31 RES INT5 T3ST TOG3 SO Modulator 3 Control M2 T3CM2 SI SC SISC Control INT3 Output SI LSB SRB Receive buffer I/O-bus ATAM894 SC SI T3O SC MCL_SC MCL_SD SI 75 ...
Page 76
... Timer 3. The SSI must be supplied with the toggle signal of Timer 2. The counter is driven by an internal or external clock source. Figure 6-56. Pulse-width Modulation Counter 3 ATAM894 76 T3R ...
Page 77
... Timer 3 Manchester demodulation/pulse-width demodulation with Timer 3 Timer 3 Synchronize mode T3I T3EX SI CM31 = SCI 1 SR-DATA BIT 0 Manchester demodulation mode BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 ATAM894 BIT 6 77 ...
Page 78
... The counter can be driven by any internal clock source and the output T3O can be used by Timer 2 in this mode. Figure 6-58. Bi-phase Demodulation CM31 = SCI ATAM894 78 8-bit shift register internal data input (SI) and the internal shift clock (SCI) from the Timer 3 Bi-phase demodulation with Timer 3 ...
Page 79
... T3I Demodu- lator 3 CM31 RES INT5 T3ST TOG3 SO Control Modulator 3 TOG2 M2 T3CM2 I/O-bus T2M2 DCGO OUTPUT 8-bit Counter 2/2 RES OVF2 MOUT TOG2 Compare 2/2 Bi-phase INT4 Manchester modulator T2CO2 SO Control SSI (RE, FE, SCO, OMSK) ATAM894 SCI SI T3O SSI T2O M2 Timer 2 modulator 2 output-stage 79 ...
Page 80
... Counter 3 CM1 CM2 TOG3 Counter 2/2 TOG2 M2 T3O ATAM894 80 T3R T3I 111213141516 TOG2 T3CP- Capture value = 0 T3R T3I 910 TOG2 ...
Page 81
... TOG3 SO Modulator 3 Control M2 TOG2 T3CM2 I/O-bus T2M2 OUTPUT OVF2 MOUT TOG2 Compare 2/2 Bi-phase INT4 Manchester modulator T2CO2 SO Control Timer 2 modulator 2 Control output-stage (RE, FE, SISC SCO, OMSK) INT3 Output SI LSB SRB Receive buffer ATAM894 SCI SI T3O SSI T2O M2 SC MCL_SC MCL_SD SI 81 ...
Page 82
... The SSI can be supplied with the toggle signal of Timer 2 or any other clock source. The Timer 3 counter is driven by an internal or external clock source. ATAM894 82 8-bit shift register internal data output (SO) to the Timer 3 ...
Page 83
... Address V control SS Mode control SCL I/O control SDA HV-generator Page 1 --> write "01h" EEPROM Page --> write "09h" 16-bit read/write buffer 8-bit data register ATAM894 ...
Page 84
... The control byte that follows the START condition determines the following operation. It consists of the 5-bit row address, 2 mode control bits and the READ/NWRITE bit that is used to control the direction of the following transfer. A '0' defines a write access and a '1' a read access. ATAM894 84 MCL Protocol SCL ...
Page 85
... EEPROM Address Control byte Ackn Data byte 512 bits and is organized 16-bit matrix each. To read ATAM894 Read/ Mode Control Bits NWrite R/NW Ackn Data byte and C 1 ...
Page 86
... If the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The master can terminate the read operation after every byte by not responding with an acknowledge (N) by issuing a stop condition. ATAM894 86 Control byte ...
Page 87
... MSB A4 A3 Row address LB(R) HB(R) LB(R+1) MSB A4 A3 Row address HB(R) LB(R) HB(R-1) no acknowledge; HB: high byte; LB: low byte, R: row address “FFh” Stop N Stop A Data byte 2 N Stop Data byte Data byte HB(R+ LB(R+ LB(R- HB(R-n) ATAM894 N Stop LSB R/ HB(R+n) LSB R/ LB(R-n) 87 ...
Page 88
... Power down current (CPU sleep, RC oscillator active, 4-MHz quartz oscillator active) Sleep current (CPU sleep, 32-kHz quartz oscillator active 4-MHz quartz oscillator inactive) Sleep current (CPU sleep, 32-kHz quartz oscillator inactive 4-MHz quartz oscillator inactive) Pin capacitance ATAM894 Symbol short ...
Page 89
... 6. 2. 3. 3. 3.0V 6.5V DD ATAM894 Symbol Min. Typ. Max. V 1.54 1.7 1.88 POR V 1.83 2.0 2.20 POR V 50 POR V 3.0 3.35 MThh V 2.77 3.0 MThh V 2.6 MThm V 2.4 2.6 MThm V 2.2 2.44 MThl V 2.0 2.2 MThl V 1.3 VMI V 1.18 1.3 VMI 0 0.8 ...
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... Power-on reset time RC-Oscillator 1 Frequency Stability RC-Oscillator 2 - External Resistor Frequency Stability Stabilization time 4-MHz Crystal Oscillator (Operating Range V Frequency Start-up time Stability Integrated input/output capacitances (configurable) ATAM894 25°C unless otherwise specified. amb Test Conditions V = 1 – amb V = 2.4 to 6.5V ...
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... IN OUT Erase-/write cycles T = 85°C amb For 16-bit access T = 85°C amb Erase-/write cycles 40°C amb OSCIN OSCOUT SCLIN SCLOUT ATAM894 Symbol Min. Typ. Max. f 32.768 X t 0.5 SQ f/f – ...
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... The designer also gains the ability to analyze the executed instruction sequences and all the I/O activities. Figure 12-1. MARC4 Emulation MARC4 emulator Program memory Trace memory Control logic Personal computer ATAM894 92 MARC4 emulation-CPU I/O bus CORE I/O control Emulation control Port 0 Port 1 SYSCL/ ...
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... Note Hardware revision Y = Lead-free 14. Package Information Package SSO24 Dimensions in mm 0.25 0. 4679D–4BMCU–05/05 Program Memory Data-EEPROM 8 kB Flash 2 512 Bit 8 kB Flash 2 512 Bit 8.05 7.80 1.30 0.15 0.05 7. ATAM894 Package Delivery SSO24 Taped and reeled SSO24 Tubes 5.7 5.3 4.5 4.3 0.15 6.6 6.3 technical drawings according to DIN specifications 93 ...
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... Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4679D-4BMCU-05/05 4679C-4BMCU-03/04 ATAM894 94 History Put datasheet in a new template Lead-free Logo on page 1 added Figure 5-2 “ROM Map” on page 5 replaced Section “ ...
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... Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 1 2 Pin Configuration ..................................................................................... 2 3 Introduction .............................................................................................. 3 4 Differences Between ATAM894 and ATARx90/x92 ............................... 3 5 MARC4 Architecture ................................................................................ 4 6 Peripheral Modules ................................................................................ 22 7 Data EEPROM ......................................................................................... 83 8 Absolute Maximum Ratings .................................................................. 88 9 Thermal Resistance ............................................................................... Operating Characteristics ............................................................... Characteristics ................................................................................. Ordering Information ............................................................................. 93 14 Package Information ............................................................................. 93 4679D– ...
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... Revision History ..................................................................................... 94 16 Table of Contents.................................................................................... 95 ATAM894 96 4679D–4BMCU–05/05 ...
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... Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2005. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...