ml67q4051 Oki Semiconductor, ml67q4051 Datasheet - Page 9

• Manufacturer Part Number: ml67q4051
• Description: 32-bit Arm -based General Purpose Microcontroller
• Manufacturer: Oki Semiconductor

June 2006, Rev 1.2
Pin Configuration
Pin Descriptions
The pins of the ML67Q4050/Q4060 Series devices have multiple uses
which are shown in detail in
page 12. The selection of function used is defined in Chapter 5 the
“ML67Q4050/Q4060 Series User’s Manual”. The following table
Pin Descriptions
SYSCLK_P
SYSCLK_N
RTCCLK_P
RTCCLK_N
RESET_N
RSTOUT_N
TEST1
TEST2
BOOT0
BOOT1
BOOTCLK
JTAGE
TCK
TMS
NTRST
TDI
TDO
BS
XA [22:0]
XD [31:0]
EXBUSE
EXIROME
OE_N
WR_N
ROMCS_N
RAMCS_N
BS0/1/2/3_N
IOCS0_N
IOCS1_N
DMAREQ
DMACLR
Symbol
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
“I/O Functions Share Pin Locations”
System Clock
32.768 kHz RTC Clock
System Reset input (Active-Low)
Reset output (Active-Low) – shares pin with PA6
System Test 1
System Test 2
Power-up default, selects boot device – shares pin with PE3
Power-up default, selects boot device – shares pin with PO4
Power-up default, Boot Clock – shares pin with PD5
Power-up default, JTAG Test Enable – shares pin with PA5
Power-up default, JTAG Clock – shares pin with PA0
Power-up default, JTAG Mode Select – shares pin with PA1
Power-up default, Resets JTAG function (Active Low) – shares pin with PA4
Power-up default, JTAG Data Input – shares pin with PA2
Power-up default, JTAG Data Output – shares pin with PA3
Power-up default, boundary scan select – shares pin with PD4
23-bit Address bus for external devices
32-bit Data bus for external devices
Power-up default, memory bus enable – shares pin with PO2
Power-up default, memory access enable – shares pin with PO3
Memory access read enable (Active-Low) – shares pin with PO0
Memory access write enable (Active-Low) – shares pin with PO1
ROM chip select (Active-Low) – shares pin with PN0
RAM chip select (Active-Low) – shares pin with PN1
Four memory byte selects (Active-Low) – shares pin with PN4/5/6/7
I/O bank 1, chip select 0 (Active-Low) – shares pin with PN2
I/O bank 1, chip select 1 (Active-Low) – shares pin with PN3
DMA request – used to request a DMA transfer – shares pin with PI5
DMA Clear – signals completion of DMA transfers – shares pin with PI6
External Memory Control Signal (ML67Q4050/4051 Only)
External DMA Control (ML67Q4050/51 Only)
Debug and Boundary Scan Support
on
System
Description
Mode
provides the description and function of the pins when they are
selected/enabled. The Functions are defined as 1st (primary) / 2nd
(secondary) / 3rd (tertiary). The “Initial Function at Reset” overrides
other functions and is used until the device is configured.
ML67Q4050/Q4060 Series
Oki Semiconductor • 9
Initial Function
at Reset
Initial Function
at Reset
Initial Function
at Reset
1st
Function Level
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
2nd
3rd
✔
✔