mc68hc05p18a Freescale Semiconductor, Inc, mc68hc05p18a Datasheet - Page 24

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mc68hc05p18a

Manufacturer Part Number
mc68hc05p18a
Description
Mc68hc05p18a Hcmos Microcontroller Unit
Manufacturer
Freescale Semiconductor, Inc
Datasheet
General Description
1.5.9 Maskable Interrupt Request (IRQ)
1.5.10 CPU Core
Technical Data
This input pin drives the asynchronous interrupt function of the MCU.
The MCU completes the current instruction being executed before it
responds to the IRQ interrupt request. When IRQ is driven low, the event
is latched internally to signify an interrupt has been requested. When the
MCU completes its current instruction, the interrupt latch is tested. If the
interrupt latch is set, and the interrupt mask bit (I bit) in the condition
code register (CCR) is clear, the MCU begins the interrupt sequence.
Depending on the mask option selected, the IRQ pin triggers this
interrupt on either a negative going edge at the IRQ pin and/or while the
IRQ pin is held in the low state. In either case, the IRQ pin must be held
low for at least one t
If the edge- and level-sensitive mask option is selected, the IRQ input
requires an external resistor connected to V
If the IRQ pin is not used, it must be tied to the V
contains an internal Schmitt trigger as part of its input circuitry to improve
noise immunity. Refer to
The MC68HC05P18A uses a standard M68HC05 series CPU core. A
description of the instruction set is in
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
General Description
ILIH
time period.
Section 4.
Interrupts.
Section 12. Instruction
DD
for a wired-OR operation.
DD
supply. The IRQ pin
MC68HC05P18A
Set.

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