mc68hc05pl4b Freescale Semiconductor, Inc, mc68hc05pl4b Datasheet - Page 73

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mc68hc05pl4b

Manufacturer Part Number
mc68hc05pl4b
Description
Low-cost Single-chip Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
12.1.11 Read-Modify-Write Instructions
12.1.12 Jump/Branch Instructions
MC68HC05PL4
REV 2.0
These instructions read a memory location or a register, modify its contents, and
write the modi ed v alue back to the memory location or to the register. The test for
negative or zero instruction (TST) is an exception to the read-modify-write
sequence because it does not write a replacement value. Table 12-2 lists the
read-modify-write instructions.
Jump instructions allow the CPU to interrupt the normal sequence of the program
counter. The unconditional jump instruction (JMP) and the jump to subroutine
instruction (JSR) have no register operand. Branch instructions allow the CPU to
interrupt the normal sequence of the program counter when a test condition is
met. If the test condition is not met, the branch is not performed. All branch
instructions use relative addressing.
Bit test and branch instructions cause a branch based on the state of any
readable bit in the rst 256 memor y locations. These three-byte instructions use a
combination of direct addressing and relative addressing. The direct address of
the byte to be tested is in the byte following the opcode. The third byte is the
signed offset byte. The CPU nds the conditional br anch destination by adding the
Freescale Semiconductor, Inc.
Arithmetic Shift Left
Arithmetic Shift Right
Clear Bit in Memory
Set Bit in Memory
Clear
Complement (One’s Complement)
Decrement
Increment
Logical Shift Left
Logical Shift Right
Negate (Two’s Complement)
Rotate Left through Carry Bit
Rotate Right through Carry Bit
Test for Negative or Zero
Table 12-2. Read-Modify-Write Instructions
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Go to: www.freescale.com
INSTRUCTION SET
Instruction
April 30, 1998
GENERAL RELEASE SPECIFICATION
Mnemonic
BCLR
BSET
COM
ROR
ASR
CLR
DEC
NEG
ROL
ASL
LSR
LSL
TST
INC
12-5

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