mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 203

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

MC68HC705V12
—
Rev. 3.0
SYNR — Synchronize Flag Reset Bit
GCS1–GCS0 — Gauge Clock Select Bits
SCNS — Scan Start Bit
current scan cycle. Any time this bit is set and the SYNIE bit is set, a
CPU interrupt will be generated. The bit will be set even if minor D is
not enabled in the GER, since the scanning sequence time is not
affected by the enabling or disabling of the gauges. This bit will
function in either auto or manual mode and does not affect the
scanning operation in any way. It serves only as a status flag. Note
that once this bit is set, the software will have a time, 2 * t
update the CDR and CMR register if new data is to be used in the next
scan cycle.
The bit is cleared by writing a 1 to the SYNR bit and by reset.
This bit is used to clear the SYNF bit. Writing a 1 to this bit will clear
the SYNF bit if the SYNF bit was set during a read of the SSCR. This
bit will always read 0.
These bits determine the clock divide ratio for the clock used by the
scan sequencer. This provides for the use of several different system
clock rates while still providing the gauge driver module with the same
scanning rate.
When the coil sequencer is being operated in manual mode, this bit is
used to initiate a scan cycle. Setting this bit starts the scan cycle. All
CMRs and CDRs will transfer data from the master to the slave when
this bit is set.
Freescale Semiconductor, Inc.
1. Must not be selected
For More Information On This Product,
Clock Frequency
f
op
f
f
f
op
op
op
CPU Bus
= 4.0 MHz
Go to: www.freescale.com
= 0.5 MHz
= 1.0 MHz
= 2.0 MHz
Table 15-2. Gauge Module Clock Select Bits
Gauge Drivers
(1)
GCS1
0
0
1
1
GCS0
0
1
0
1
Division
Coil Sequencer and Control
1024
2048
4096
512
Advance Information
Gauge Drivers
Scan Cycle
GCS,
Time
t
t
t
t
GCS
GCS
GCS
GCS
to