mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 92

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mc68hc708mp16

Manufacturer Part Number
mc68hc708mp16
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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System Integration Module (SIM)
7.6 Exception Control
7.6.1 Interrupts
Technical Data
92
I BIT
R/W
IAB
IDB
INTERRUPT
MODULE
DUMMY
DUMMY
Normal, sequential program execution can be changed in three different
ways:
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
Figure 7-10
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared).
(See
SP
PC – 1[7:0]
Figure
Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
Reset
Break interrupts
SP – 1
Figure 7-8
PC – 1[15:8]
System Integration Module (SIM)
shows interrupt recovery timing.
7-9.)
SP – 2
X
.
SP – 3
Interrupt Entry
Figure 7-8
A
SP – 4
CCR
shows interrupt entry timing.
VECT H
V DATA H
VECT L
MC68HC708MP16
V DATA L
Freescale Semiconductor
START ADDR
OPCODE
Rev. 3.1

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