mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 205

• Manufacturer Part Number: mc68ec060
• Description: Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
• Manufacturer: Freescale Semiconductor, Inc

Bus Operation
The MC68060 considers the resulting second, third, and fourth long-word bus cycles of a
burst-inhibited line transfer as part of the original line transfer cycle. Therefore, the MC68060
interprets a retry termination during these bus cycles as though they were part of the original
line transfer, and depending on the acknowledge termination mode, a retry termination is
either interpreted as a bus error (MC68040 mode) or ignored (native-MC68060 mode).
Negating the bus grant (BG) signal on the MC68060 while indicating a retry termination pro-
vides a relinquish and retry operation for any bus cycle that can be retried (see Figure 7-44).
If retrying a bus cycle that is part of a locked sequence of bus cycles, a relinquish and retry
of the bus requires BGR be asserted along with BG negated to cause the processor to abort
any following locked bus cycles that are a part of the locked sequence.
7-50
NATIVE-MC68060
ACKNOWLEDGE
ACKNOWLEDGE
TERMINATION
TERMINATION
MC68040
MISCELLANEOUS
MODE
MODE
ATTRIBUTES
SIZ1–SIZ0
Figure 7-39. Retry Read Bus Cycle Timing
A31–A0
D31–D0
BCLK
R/W
TEA
TEA
SAS
TIP
TRA
TRA
TS
TA
TA
M68060 USER’S MANUAL
C1
RETRY SIGNALED
READ CYCLE
CW
C2
LONG
C1
RETRY
CYCLE
C2
MOTOROLA